Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics

Logic Computing Field-Effect Transistors Based on a Monolayer WSe2 Homojunction for the Semi-adder and Decoder

Two-dimensional reconfigurable field-effect transistors (FETs) are promising candidates for next-generation computing hardware. However, exploring the cascade design of FETs for logic computing remains challenging. Here, by using density functional theory combined with the nonequilibrium Green's function method, we design a 5 nm split-gate FET based on a monolayer WSe2 homojunction, which can implement dynamic polarity control in different gate configurations. The series array of two FETs shows a functional family of logic gates (NOR, AND, XOR, A̅B, and AB̅), and the semi-adder designed by the logic functions AND and XOR reduces the number of transistors by 66.7%. The parallel array of two FETs demonstrates reconfigurable logic gates with NAND/OR/A̅+B/A+B̅ quadruple functions, which can realize the decoding function of 00-11 in the decoder. The cascade design of the electrically tunable FETs helps to tackle the logic device downscaling and integration dilemmas.

Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlOx/Al2O3 and a double-gate structure employing high-k dielectric HfO2. Due to the superior subthreshold characteristics, monolayer WS2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage (VDD) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm-1 at VDD = 1 V. In addition, the monolayer WS2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS2 for high-gain and low-power logic circuits and validate the practical application in large areas.

Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics

Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm-2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS2 transistors exhibiting high on/off current ratios over 108, ultralow subthreshold swing of 65 mV dec-1 and ultralow leakage current density of ~10-6 A cm-2. Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor-insulator transition at the clean-limit Bi2Sr2CaCu2O8+δ can also be realized through fluoride gating. Our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40 nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7 nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

The Roadmap of 2D Materials and Devices Toward Chips

Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked.

12-inch growth of uniform MoS2 monolayer for integrated circuit manufacture

Two-dimensional (2D) semiconductors, such as transition metal dichalcogenides, provide an opportunity for beyond-silicon exploration. However, the lab to fab transition of 2D semiconductors is still in its preliminary stages, and it has been challenging to meet manufacturing standards of stability and repeatability. Thus, there is a natural eagerness to grow wafer-level, high-quality films with industrially acceptable scale-cost-performance metrics. Here we report an improved chemical vapour deposition synthesis method in which the controlled release of precursors and substrates predeposited with amorphous Al2O3 ensure the uniform synthesis of monolayer MoS2 as large as 12 inches while also enabling fast and non-toxic growth to reduce manufacturing costs. Transistor arrays were fabricated to further confirm the high quality of the film and its integrated circuit application potential. This work achieves the co-optimization of scale-cost-performance metrics and lays the foundation for advancing the integration of 2D semiconductors in industry-standard pilot lines.

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array.

Large-Scale Complementary Logic Circuit Enabled by Al2O3 Passivation-Induced Carrier Polarity Modulation in Tungsten Diselenide

Achieving effective polarity control of n- and p-type transistors based on two-dimensional (2D) materials is a critical challenge in the process of integrating transition metal dichalcogenides (TMDC) into complementary metal-oxide semiconductor (CMOS) logic circuits. Herein, we utilized a proficient and nondestructive method of electron-charge transfer to achieve a complete carrier polarity conversion from p-to n-type by depositing a thin layer of aluminum oxide (Al2O3) onto tungsten diselenide (WSe2). By utilizing the Al2O3 passivation layer, we observed precisely tuned n-type behavior in contrast to transistors fabricated on the as-grown WSe2 film without any passivation layer, which display prominent p-type behavior. The polarity-transformed n-type WSe2 transistor from the pristine p-type shows the maximum ON current of ∼0.1 μA accompanied by a high electron mobility of 7 cm2 V-1 s-1 at a drain voltage (VDS) of 1 V. We successfully showcased a homogeneous CMOS inverter utilizing 2D-TMDC which exhibits an impressive voltage gain of 7 at VDD = 5 V. Moreover, this effective polarity control approach was further expanded upon to successfully demonstrate a range of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. The proposed methodology possesses significant promise for facilitating the advancement of high-density circuitry components utilizing 2D-TMDC.

Reconfigurable Logic-in-Memory Computing Based on a Polarity-Controllable Two-Dimensional Transistor

Logic-in-memory architecture holds great promise to meet the high-performance and energy-efficient requirements of data-intensive scenarios. Two-dimensional compacted transistors embedded with logic functions are expected to extend Moore's law toward advanced nodes. Here we demonstrate that a WSe₂/h-BN/graphene based middle-floating-gate field-effect transistor can perform under diverse current levels due to the controllable polarity by the control gate, floating gate, and drain voltages. Such electrical tunable characteristics are employed for logic-in-memory architectures and can behave as reconfigurable logic functions of AND/XNOR within a single device. Compared to the conventional devices like floating-gate field-effect transistors, our design can greatly decrease the consumption of transistors. For AND/NAND, it can save 75% transistors by reducing the transistor number from 4 to 1; for XNOR/XOR, it is even up to 87.5% with the number being reduced from 8 to 1.

Optically Reconfigurable Complementary Logic Gates Enabled by Bipolar Photoresponse in Gallium Selenide Memtransistor

To avoid the complexity of the circuit for in-memory computing, simultaneous execution of multiple logic gates (OR, AND, NOR, and NAND) and memory behavior are demonstrated in a single device of oxygen plasma-treated gallium selenide (GaSe) memtransistor. Resistive switching behavior with R_ON /R_OFF ratio in the range of 10⁴ to 10⁶ is obtained depending on the channel length (150 to 1600 nm). Oxygen plasma treatment on GaSe film created shallow and deep-level defect states, which exhibit carriers trapping/de-trapping, that lead to negative and positive photoconductance at positive and negative gate voltages, respectively. This distinguishing feature of gate-dependent transition of negative to positive photoconductance encourages the execution of four logic gates in the single memory device, which is elusive in conventional memtransistor. Additionally, it is feasible to reversibly switch between two logic gates by just adjusting the gate voltages, e.g., NAND/NOR and AND/NAND. All logic gates presented high stability. Additionally, memtransistor array (1×8) is fabricated and programmed into binary bits representing ASCII (American Standard Code for Information Interchange) code for the uppercase letter "N". This facile device configuration can provide the functionality of both logic and memory devices for emerging neuromorphic computing.

Comparative Study between Sulfurized MoS2 from Molybdenum and Molybdenum Trioxide Precursors for Thin-Film Device Applications

Two-dimensional (2D) materials have been studied as an emerging class of nanomaterials owing to their attractive properties in nearly every field of science and technology. Molybdenum disulfide (MoS₂) is one of the more promising candidates of these atomically thin 2D materials for its technological potential. The facile synthesis of MoS₂ remains a matter of broad interest. In this study, MoS₂ was synthesized by chemical vapor deposition sulfurization at various temperatures (550 °C, 650 °C, and 750 °C) of either precursor molybdenum metal (Mo) or molybdenum trioxide (MoO₃) deposited on silicon/silicon dioxide (Si/SiO₂) via e-beam evaporation. Monolayer, bilayer, and few layers sulfurized samples have been grown and verified by Raman, photoluminescence spectroscopy, XRD, XPS, and AFM. MoO₃ sulfurization provided monolayer growth in comparison to Mo sulfurization under the same conditions and precursor thicknesses. Optical microscopy showed the homogeneous nature of grown samples. A main finding of this work is that MoO₃ sulfurization produced higher quality MoS₂ as compared to those grown by an Mo precursor. Device characteristics based on monolayer MoO₃ sulfurized MoS_2-x include nonvolatile resistive switching with I_on/I_off ≈ 10⁴ at a relatively low operating bias of ±1 V. In addition, field-effect transistor characteristics revealed p-type material growth with a carrier mobility ∼ 41 cm² V^-1 s^-1, which is in contrast to typically observed n-type characteristics.

Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling

This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal-oxide-semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe₂) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10^-5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe₂ SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors

2D semiconductors, such as molybdenum disulfide (MoS₂ ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS₂ film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS₂ field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS₂ logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

Nonvolatile Logic and Ternary Content-Addressable Memory Based on Complementary Black Phosphorus and Rhenium Disulfide Transistors

Hardware realization of in-memory computing for efficient data-intensive computation is regarded as a promising paradigm beyond the Moore era. However, to realize such functions, the device structure using traditional Si complementary metal-oxide-semiconductor (CMOS) technology is complex with a large footprint. 2D material-based heterostructures have a unique advantage to build versatile logic functions based on novel heterostructures with simplified device footprint and low power. Here, by adopting the charge-trapping mechanism between a black phosphorus (BP) channel and a phosphorus oxide (PO_x ) layer, a nonvolatile CMOS logic circuit based on 2D BP and rhenium disulfide (ReS₂ ) with a high voltage gain of ≈275 is realized with a persistent hysteresis window. A Schmidt-like flip-flop using only two transistors is also demonstrated, with far fewer transistor numbers than the conventional silicon counterpart, which usually requires six transistors. Furthermore, four-transistor (4T) nonvolatile ternary content-addressable memory (nvTCAM) cells are demonstrated with far fewer transistors for parallel data search. The nvTCAM cells exhibit high resistance ratios (R_ratio ) up to ≈10³ between match and mismatch states with zero standby power thanks to the nonvolatility of the BP transistors. This back-end-of-line compatible nvTCAM shows advantages over other structures with reduced complexity and thermal budget.

Two-dimensional devices and integration towards the silicon lines

Despite technical efforts and upgrades, advances in complementary metal-oxide-semiconductor circuits have become unsustainable in the face of inherent silicon limits. New materials are being sought to compensate for silicon deficiencies, and two-dimensional materials are considered promising candidates due to their atomically thin structures and exotic physical properties. However, a potentially applicable method for incorporating two-dimensional materials into silicon platforms remains to be illustrated. Here we try to bridge two-dimensional materials and silicon technology, from integrated devices to monolithic 'on-silicon' (silicon as the substrate) and 'with-silicon' (silicon as a functional component) circuits, and discuss the corresponding requirements for material synthesis, device design and circuitry integration. Finally, we summarize the role played by two-dimensional materials in the silicon-dominated semiconductor industry and suggest the way forward, as well as the technologies that are expected to become mainstream in the near future.

Surface Passivation of Layered MoSe2 via van der Waals Stacking of Amorphous Hydrocarbon

Development of efficient surface passivation methods for semiconductor devices is crucial to counter the degradation in their electrical performance owing to scattering or trapping of carriers in the channels induced by molecular adsorption from the ambient environment. However, conventional dielectric deposition involves the formation of additional interfacial defects associated with broken covalent bonds, resulting in accidental electrostatic doping or enhanced hysteretic behavior. In this study, centimeter-scaled van der Waals passivation of transition metal dichalcogenides (TMDCs) is demonstrated by stacking hydrocarbon (HC) dielectrics onto MoSe₂ field-effect transistors (FETs), thereby enhancing the electric performance and stability of the device, accompanied with the suppression of chemical disorder at the HC/TMDCs interface. The stacking of HC onto MoSe₂ FETs enhances the carrier mobility of MoSe₂ FET by over 50% at the n-branch, and a significant decrease in hysteresis, owing to the screening of molecular adsorption. The electron mobility and hysteresis of the HC/MoSe₂ FETs are verified to be nearly intact compared to those of the fabricated HC/MoSe₂ FETs after exposure to ambient environment for 3 months. Consequently, the proposed design can act as a model for developing advanced nanoelectronics applications based on layered materials for mass production.

A 619-pixel machine vision enhancement chip based on two-dimensional semiconductors

The rapid development of machine vision applications demands hardware that can sense and process visual information in a single monolithic unit to avoid redundant data transfer. Here, we design and demonstrate a monolithic vision enhancement chip with light-sensing, memory, digital-to-analog conversion, and processing functions by implementing a 619-pixel with 8582 transistors and physical dimensions of 10 mm by 10 mm based on a wafer-scale two-dimensional (2D) monolayer molybdenum disulfide (MoS₂). The light-sensing function with analog MoS₂ transistor circuits offers low noise and high photosensitivity. Furthermore, we adopt a MoS₂ analog processing circuit to dynamically adjust the photocurrent of individual imaging sensor, which yields a high dynamic light-sensing range greater than 90 decibels. The vision chip allows the applications for contrast enhancement and noise reduction of image processing. This large-scale monolithic chip based on 2D semiconductors shows multiple functions with light sensing, memory, and processing for artificial machine vision applications, exhibiting the potentials of 2D semiconductors for future electronics.

Strategies for Controlled Growth of Transition Metal Dichalcogenides by Chemical Vapor Deposition for Integrated Electronics

In recent years, transition metal dichalcogenide (TMD)-based electronics have experienced a prosperous stage of development, and some considerable applications include field-effect transistors, photodetectors, and light-emitting diodes. Chemical vapor deposition (CVD), a typical bottom-up approach for preparing 2D materials, is widely used to synthesize large-area 2D TMD films and is a promising method for mass production to implement them for practical applications. In this review, we investigate recent progress in controlled CVD growth of 2D TMDs, aiming for controlled nucleation and orientation, using various CVD strategies such as choice of precursors or substrates, process optimization, and system engineering. We then survey different patterning methods, such as surface patterning, metal precursor patterning, and postgrowth sulfurization/selenization/tellurization, to mass produce heterostructures for device applications. With these strategies, various well-designed architectures, such as wafer-scale single crystals, vertical and lateral heterostructures, patterned structures, and arrays, are achieved. In addition, we further discuss various electronics made from CVD-grown TMDs to demonstrate the diverse application scenarios. Finally, perspectives regarding the current challenges of controlled CVD growth of 2D TMDs are also suggested.

All-in-one, bio-inspired, and low-power crypto engines for near-sensor security based on two-dimensional memtransistors

In the emerging era of the internet of things (IoT), ubiquitous sensors continuously collect, consume, store, and communicate a huge volume of information which is becoming increasingly vulnerable to theft and misuse. Modern software cryptosystems require extensive computational infrastructure for implementing ciphering algorithms, making them difficult to be adopted by IoT edge sensors that operate with limited hardware resources and at low energy budgets. Here we propose and experimentally demonstrate an “all-in-one” 8 × 8 array of robust, low-power, and bio-inspired crypto engines monolithically integrated with IoT edge sensors based on two-dimensional (2D) memtransistors. Each engine comprises five 2D memtransistors to accomplish sensing and encoding functionalities. The ciphered information is shown to be secure from an eavesdropper with finite resources and access to deep neural networks. Our hardware platform consists of a total of 320 fully integrated monolayer MoS₂-based memtransistors and consumes energy in the range of hundreds of picojoules and offers near-sensor security.

Internet of things (IoT) sensors can collect, store and communicate large volumes of information, which require effective security measures. Here, the authors report the realization of low-power edge sensors based on photosensitive and programmable 2D memtransistors, integrating sensing, storage and encryption functionalities.

Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire

Two-dimensional transition-metal dichalcogenides (TMDs) are of interest for beyond-silicon electronics^1,2. It has been suggested that bilayer TMDs, which combine good electrostatic control, smaller bandgap and higher mobility than monolayers, could potentially provide improvements in the energy-delay product of transistors^3-5. However, despite advances in the growth of monolayer TMDs^6-14, the controlled epitaxial growth of multilayers remains a challenge¹⁵. Here we report the uniform nucleation (>99%) of bilayer molybdenum disulfide (MoS₂) on c-plane sapphire. In particular, we engineer the atomic terrace height on c-plane sapphire to enable an edge-nucleation mechanism and the coalescence of MoS₂ domains into continuous, centimetre-scale films. Fabricated field-effect transistor (FET) devices based on bilayer MoS₂ channels show substantial improvements in mobility (up to 122.6 cm² V^-1 s^-1) and variation compared with FETs based on monolayer films. Furthermore, short-channel FETs exhibit an on-state current of 1.27 mA μm^-1, which exceeds the 2028 roadmap target for high-performance FETs¹⁶.

Engineering Top Gate Stack for Wafer-Scale Integrated Circuit Fabrication Based on Two-Dimensional Semiconductors

In recent years, two-dimensional (2D) semiconductors have attracted considerable attention from both academic and industrial communities. Recent research has begun transforming from constructing basic field-effect transistors (FETs) into designing functional circuits. However, device processing remains a bottleneck in circuit-level integration. In this work, a non-destructive doping strategy is proposed to modulate precisely the threshold voltage (V_TH) of MoS₂-FETs in a wafer scale. By inserting an Al interlayer with a varied thickness between the high-k dielectric and the Au top gate (TG), the doping could be controlled. The full oxidation of the Al interlayer generates a surplus of oxygen vacancy (Vo) in the high-k dielectric layer, which further leads to stable electron doping. The proposed strategy is then used to optimize an inverter circuit by matching the electrical properties of the load and driver transistors. Furthermore, the doping strategy is used to fabricate digital logic blocks with desired logic functions, which indicates its potential to fabricate fully integrated multistage logic circuits based on wafer-scale 2D semiconductors.

Analysis of Schottky barrier heights and reduced Fermi-level pinning in monolayer CVD-grown MoS2field-effect-transistors

Chemical vapor deposition (CVD)-grown monolayer (ML) molybdenum disulfide (MoS₂) is a promising material for next-generation integrated electronic systems due to its capability of high-throughput synthesis and compatibility with wafer-scale fabrication. Several studies have described the importance of Schottky barriers in analyzing the transport properties and electrical characteristics of MoS₂field-effect-transistors (FETs) with metal contacts. However, the analysis is typically limited to single devices constructed from exfoliated flakes and should be verified for large-area fabrication methods. In this paper, CVD-grown ML MoS₂was utilized to fabricate large-area (1 cm × 1 cm) FET arrays. Two different types of metal contacts (i.e. Cr/Au and Ti/Au) were used to analyze the temperature-dependent electrical characteristics of ML MoS₂FETs and their corresponding Schottky barrier characteristics. Statistical analysis provides new insight about the properties of metal contacts on CVD-grown MoS₂compared to exfoliated samples. Reduced Schottky barrier heights (SBH) are obtained compared to exfoliated flakes, attributed to a defect-induced enhancement in metallization of CVD-grown samples. Moreover, the dependence of SBH on metal work function indicates a reduction in Fermi level pinning compared to exfoliated flakes, moving towards the Schottky-Mott limit. Optical characterization reveals higher defect concentrations in CVD-grown samples supporting a defect-induced metallization enhancement effect consistent with the electrical SBH experiments.

An artificial neural network chip based on two-dimensional semiconductor

Recently, research on two-dimensional (2D) semiconductors has begun to translate from the fundamental investigation into rudimentary functional circuits. In this work, we unveil the first functional MoS₂ artificial neural network (ANN) chip, including multiply-and-accumulate (MAC), memory and activation function circuits. Such MoS₂ ANN chip is realized through fabricating 818 field-effect transistors (FETs) on a wafer-scale and high-homogeneity MoS₂ film, with a gate-last process to realize top gate structured FETs. A 62-level simulation program with integrated circuit emphasis (SPICE) model is utilized to design and optimize our analog ANN circuits. To demonstrate a practical application, a tactile digit sensing recognition was demonstrated based on our ANN circuits. After training, the digit recognition rate exceeds 97%. Our work not only demonstrates the protentional of 2D semiconductors in wafer-scale integrated circuits, but also paves the way for its future application in AI computation.

An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions

With the rapid development of artificial intelligence, parallel image processing is becoming an increasingly important ability of computing hardware. To meet the requirements of various image processing tasks, the basic pixel processing unit contains multiple functional logic gates and a multiplexer, which leads to notable circuit redundancy. The pixel processing unit retains a large optimizing space to solve the area redundancy issues in parallel computing. Here, we demonstrate a pixel processing unit based on a single WSe₂ transistor that has multiple logic functions (AND and XNOR) that are electrically switchable. We further integrate these pixel processing units into a low transistor-consumption image processing array, where both image intersection and image comparison tasks can be performed. Owing to the same image processing power, the consumption of transistors in our image processing unit is less than 16% of traditional circuits.

Reducing circuit redundancy represents a priority for the scalability of parallel computing hardware. Here, the authors report the realization of pixel processing units consisting of single 2D WSe₂ transistors implementing electrically-switchable logic functions. This strategy enables the fabrication of an image processing array with ~16% transistor consumption compared to traditional circuits.

Secure Electronics Enabled by Atomically Thin and Photosensitive Two-Dimensional Memtransistors

The rapid proliferation of security compromised hardware in today's integrated circuit (IC) supply chain poses a global threat to the reliability of communication, computing, and control systems. While there have been significant advancements in detection and avoidance of security breaches, current top-down approaches are mostly inadequate, inefficient, often inconclusive, and resource extensive in time, energy, and cost, offering tremendous scope for innovation in this field. Here, we introduce an energy and area efficient non-von Neumann hardware platform providing comprehensive and bottom-up security solutions by exploiting inherent device-to-device variation, electrical programmability, and persistent photoconductivity demonstrated by atomically thin two-dimensional memtransistors. We realize diverse security primitives including physically unclonable function, anticounterfeit measures, intellectual property (IP) watermarking, and IC camouflaging to prevent false authentication, detect recycled and remarked ICs, protect IP theft, and stop reverse engineering of ICs.

Three-dimensional monolithic micro-LED display driven by atomically thin transistor matrix

Two-dimensional materials are promising candidates for future electronics due to unmatched device performance at atomic limit and low-temperature heterogeneous integration. To adopt these emerging materials in computing and optoelectronic systems, back end of line (BEOL) integration with mainstream technologies is needed. Here, we show the integration of large-area MoS₂ thin-film transistors (TFTs) with nitride micro light-emitting diodes (LEDs) through a BEOL process and demonstrate high-resolution displays. The MoS₂ transistors exhibit median mobility of 54 cm² V^-1s ^-1, 210 μA μm^-1 drive current and excellent uniformity. The TFTs can drive micrometre-sized LEDs to 7.1 × 10⁷ cd m^-2 luminance under low voltage. Comprehensive analysis on driving capability, response time, power consumption and modulation scheme indicates that MoS₂ TFTs are suitable for a range of display applications up to the high resolution and brightness limit. We further demonstrate prototypical 32 × 32 active-matrix displays at 1,270 pixels-per-inch resolution. Moreover, our process is fully monolithic, low-temperature, scalable and compatible with microelectronic processing.

Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS₂ top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS₂ FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials.

Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.

SynCells: A 60 × 60 μm2 Electronic Platform with Remote Actuation for Sensing Applications in Constrained Environments

Autonomous electronic microsystems smaller than the diameter of a human hair (<100 μm) are promising for sensing in confined spaces such as microfluidic channels or the human body. However, they are difficult to implement due to fabrication challenges and limited power budget. Here we present a 60 × 60 μm electronic microsystem platform, or SynCell, that overcomes these issues by leveraging the integration capabilities of two-dimensional material circuits and the low power consumption of passive germanium timers, memory-like chemical sensors, and magnetic pads. In a proof-of-concept experiment, we magnetically positioned SynCells in a microfluidic channel to detect putrescine. After we extracted them from the channel, we successfully read out the timer and sensor signal, the latter of which can be amplified by an onboard transistor circuit. The concepts developed here will be applicable to microsystems targeting a variety of applications from microfluidic sensing to biomedical research.

PtS2 nanosheets as a peroxidase-mimicking nanozyme for colorimetric determination of hydrogen peroxide and glucose

Using an ultrasonication-assisted liquid exfoliation method, we have synthesized PtS2 nanosheets with good reproducibility. Herein, intrinsic peroxidase-like activity was for the first time demonstrated for PtS2 nanosheets, which can catalyze H2O2 oxidation of 3,3',5,5'-tetramethylbenzidine (TMB) to generate a colored solution. The catalytic mechanism of PtS2 nanosheets was investigated, which indicated that acceleration of the electron transfer between TMB and H2O2 was the main reason for the peroxidase-like activity of PtS2 nanosheets. Based on these observations, we exploited PtS2 nanosheets integrated into dopamine-functionalized hyaluronic acid (HA-DA) hydrogel microspheres by droplet microfluidics to construct PtS2 nanosheet- and PtS2@HA-DA microsphere-based sensors for highly sensitive determination of H2O2. When coupled with glucose oxidase, we further developed two glucose sensors based on the above two methods. Among them, the linearity of the PtS2 nanosheet-based spectrophotometry was in the range of 0.5 to 150 μM and the limit of detection as low as 0.20 μM. The linearity of the microsphere-based colorimetry was in the range 200 to 12,000 μM with a detection limit of 29.95 μM. Both of the glucose sensors can be applied to the determination of glucose in human serum with reliable results and reproducibility.

Selective Pattern Growth of Atomically Thin MoSe2 Films via a Surface-Mediated Liquid-Phase Promoter

Two-dimensional transition metal dichalcogenides (TMDs) offer numerous advantages over silicon-based application in terms of atomically thin geometry, excellent opto-electrical properties, layer-number dependence, band gap variability, and lack of dangling bonds. The production of high-quality and large-scale TMD films is required with consideration of practical technology. However, the performance of scalable devices is affected by problems such as contamination and patterning arising from device processing; this is followed by an etching step, which normally damages the TMD film. Herein, we report the direct growth of MoSe₂ films on selective pattern areas via a surface-mediated liquid-phase promoter using a solution-based approach. Our growth process utilizes the promoter on the selective pattern area by enhancing wettability, resulting in a highly uniform MoSe₂ film. Moreover, our approach can produce other TMD films such as WSe₂ films as well as control various pattern shapes, sizes, and large-scale areas, thus improving their applicability in various devices in the future. Our patterned MoSe₂ field-effect transistor device exhibits a p-type dominant conduction behavior with a high on/off current ratio of ∼10⁶. Thus, our study provides general guidance for direct selective pattern growth via a solution-based approach and the future design of integrated devices for a large-scale application.

A wafer-scale synthesis of monolayer MoS2 and their field-effect transistors toward practical applications

Molybdenum disulfide (MoS2) has attracted considerable research interest as a promising candidate for downscaling integrated electronics due to the special two-dimensional structure and unique physicochemical properties. However, it is still challenging to achieve large-area MoS2 monolayers with desired material quality and electrical properties to fulfill the requirement for practical applications. Recently, a variety of investigations have focused on wafer-scale monolayer MoS2 synthesis with high-quality. The 2D MoS2 field-effect transistor (MoS2-FET) array with different configurations utilizes the high-quality MoS2 film as channels and exhibits favorable performance. In this review, we illustrated the latest research advances in wafer-scale monolayer MoS2 synthesis by different methods, including Au-assisted exfoliation, CVD, thin film sulfurization, MOCVD, ALD, VLS method, and the thermolysis of thiosalts. Then, an overview of MoS2-FET developments was provided based on large-area MoS2 film with different device configurations and performances. The different applications of MoS2-FET in logic circuits, basic memory devices, and integrated photodetectors were also summarized. Lastly, we considered the perspective and challenges based on wafer-scale monolayer MoS2 synthesis and MoS2-FET for developing practical applications in next-generation integrated electronics and flexible optoelectronics.

Formaldehyde Molecules Adsorption on Zn Doped Monolayer MoS2: A First-Principles Calculation

Based on the first principles of density functional theory, the adsorption behavior of H2CO on original monolayer MoS2 and Zn doped monolayer MoS2 was studied. The results show that the adsorption of H2CO on the original monolayer MoS2 is very weak, and the electronic structure of the substrate changes little after adsorption. A new kind of surface single cluster catalyst was formed after Zn doped monolayer MoS2, where the ZnMo3 small clusters made the surface have high selectivity. The adsorption behavior of H2CO on Zn doped monolayer MoS2 can be divided into two situations. When the H-end of H2CO molecule in the adsorption structure is downward, the adsorption energy is only 0.11 and 0.15 eV and the electronic structure of adsorbed substrate changes smaller. When the O-end of H2CO molecule is downward, the interaction between H2CO and the doped MoS2 is strong leading to the chemical adsorption with the adsorption energy of 0.80 and 0.98 eV. For the O-end-down structure, the adsorption obviously introduces new impurity states into the band gap or results in the redistribution of the original impurity states. All of these may lead to the change of the chemical properties of the doped MoS2 monolayer, which can be used to detect the adsorbed H2CO molecules. The results show that the introduction of appropriate dopant may be a feasible method to improve the performance of MoS2 gas sensor.

Layer thickness influenced irradiation effects of proton beam on MoS2 field effect transistors

We investigated the influence of the flake thickness for molybdenum disulfide (MoS₂) field effect transistors on the effect of a 150 keV high-energy proton beam applied on these devices. The electrical characteristics of the devices with channel thicknesses ranging from monolayer to bulk were measured before and after proton irradiation with a proton fluence of 5 × 10¹⁴ cm^-2. The subthreshold swing (SS), threshold voltage shift and electron mobility were extracted with the Y-function method after proton irradiation and significant degradation were observed. It is found that, with the increase of layer thickness, mobility degradation and threshold voltage shift both eased, but the SS degradation was insensitive to the MoS₂ flake thickness increase. We also demonstrate that the threshold voltage shift is dominated by oxide charges; however, the mobility and SS degradations are mainly affected by the interface traps. Our study will enhance the understanding of the influence of high-energy particles on MoS₂-based nano-electronic devices. By increasing the MoS₂ flake thickness to a certain extent, one can hopefully find a balance between effectively resisting [Formula: see text] shift and achieving high mobility and small SS degradation.

Hidden Vacancy Benefit in Monolayer 2D Semiconductors

Monolayer 2D semiconductors (e.g., MoS₂ ) are of considerable interest for atomically thin transistors but generally limited by insufficient carrier mobility or driving current. Minimizing the lattice defects in 2D semiconductors represents a common strategy to improve their electronic properties, but has met with limited success to date. Herein, a hidden benefit of the atomic vacancies in monolayer 2D semiconductors to push their performance limit is reported. By purposely tailoring the sulfur vacancies (SVs) to an optimum density of 4.7% in monolayer MoS₂ , an unusual mobility enhancement is obtained and a record-high carrier mobility (>115 cm² V^-1 s^-1 ) is achieved, realizing monolayer MoS₂ transistors with an exceptional current density (>0.60 mA µm^-1 ) and a record-high on/off ratio >10¹⁰ , and enabling a logic inverter with an ultrahigh voltage gain >100. The systematic transport studies reveal that the counterintuitive vacancy-enhanced transport originates from a nearest-neighbor hopping conduction model, in which an optimum SV density is essential for maximizing the charge hopping probability. Lastly, the vacancy benefit into other monolayer 2D semiconductors is further generalized; thus, a general strategy for tailoring the charge transport properties of monolayer materials is defined.

Benchmarking monolayer MoS2 and WS2 field-effect transistors

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS₂ and WS₂ films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS₂ FETs and 160 WS₂ FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm² chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm² V^-1 s^-1 in WS₂ FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits.

MoS2-on-AlN Enables High-Performance MoS2 Field-Effect Transistors through Strain Engineering

Molybdenum disulfide (MoS₂) has substantial application prospects in the field of electronic devices. The fabrication of devices of excellent quality based on MoS₂ films is an important research direction. In this study, based on the atomic layer deposition technique, large-area MoS₂ films were grown, and top-gate MoS₂-based field-effect transistor arrays were fabricated on four substrates (AlN, GaN, sapphire, and SiO₂). It was found that the interface defects that were introduced by lattice mismatch and roughness of the growth substrate could cause an exponential (10²) drop in mobility. Because of the small lattice mismatch and excellent surface quality, transistors on the AlN substrate have shown an enhanced mobility (10.45 cm² V^-1 s^-1) compared to transistors on the other substrates. This study proves that the AlN substrate is a superior substrate for large-area and high-performance MoS₂ film synthesis. This result can also be applied in higher-level microelectronic systems, such as in digital logic circuit design.

An Atomically Thin Optoelectronic Machine Vision Processor

2D semiconductors, especially transition metal dichalcogenide (TMD) monolayers, are extensively studied for electronic and optoelectronic applications. Beyond intensive studies on single transistors and photodetectors, the recent advent of large-area synthesis of these atomically thin layers has paved the way for 2D integrated circuits, such as digital logic circuits and image sensors, achieving an integration level of ≈100 devices thus far. Here, a decisive advance in 2D integrated circuits is reported, where the device integration scale is increased by tenfold and the functional complexity of 2D electronics is propelled to an unprecedented level. Concretely, an analog optoelectronic processor inspired by biological vision is developed, where 32 × 32 = 1024 MoS₂ photosensitive field-effect transistors manifesting persistent photoconductivity (PPC) effects are arranged in a crossbar array. This optoelectronic processor with PPC memory mimics two core functions of human vision: it captures and stores an optical image into electrical data, like the eye and optic nerve chain, and then recognizes this electrical form of the captured image, like the brain, by executing analog in-memory neural net computing. In the highlight demonstration, the MoS₂ FET crossbar array optically images 1000 handwritten digits and electrically recognizes these imaged data with 94% accuracy.

Effects of Charge Trapping at the MoS2-SiO2 Interface on the Stability of Subthreshold Swing of MoS2 Field Effect Transistors

The stability of the subthreshold swing (SS) is quite important for switch and memory applications in logic circuits. The SS in our MoS₂ field effect transistor (FET) is enlarged when the gate voltage sweep range expands towards the negative direction. This is quite different from other reported MoS₂ FETs whose SS is almost constant while varying gate voltage sweep range. This anomalous SS enlargement can be attributed to interface states at the MoS₂-SiO₂ interface. Moreover, a deviation of SS from its linear relationship with temperature is found. We relate this deviation to two main reasons, the energetic distribution of interface states and Fermi level shift originated from the thermal activation. Our study may be helpful for the future modification of the MoS₂ FET that is applied in the low power consumption devices and circuits.

Optimizing Al-doped ZrO2 as the gate dielectric for MoS2 field-effect transistors

In this work, we investigate the effects on the electrical properties of few-layered MoS₂ field-effect transistors (FETs) following Al incorporation into ZrO₂ as the gate dielectrics of the devices. A large improvement in device performance is achieved with the Al-doped ZrO₂ gate dielectric when Zr:Al = 1:1. The relevant MoS₂ transistor exhibits the best electrical characteristics: high carrier mobility of 40.6 cm² V^-1 s^-1 (41% higher than that of the control sample, and an intrinsic mobility of 68.0 cm² V^-1 s^-1), a small subthreshold swing of 143 mV dec^-1, high on/off current ratio of 6 × 10⁶ and small threshold voltage of 0.71 V. These are attributed to the facts that (i) Al incorporation into ZrO₂ can decrease its oxygen vacancies; densify the dielectric film; and smooth the gate dielectric surface, thus reducing the traps at/near the Zr_0.5Al_0.5O _y /MoS₂ interface and the gate leakage current; (ii) adjusting the dielectric constant of the gate dielectric to an appropriate value, which achieves a reasonable trade-off between the gate screening effect on the Coulomb-impurity scattering and the surface optical phonon scattering. These results demonstrate that optimized Zr_0.5Al_0.5O_y is a potential gate dielectric material for MoS₂ FET applications.

Material-Selective Doping of 2D TMDC through AlxOy Encapsulation

For the integration of two-dimensional (2D) transition metal dichalcogenides (TMDC) with high-performance electronic systems, one of the greatest challenges is the realization of doping and comprehension of its mechanisms. Low-temperature atomic layer deposition of aluminum oxide is found to n-dope MoS₂ and ReS₂ but not WS₂. Based on electrical, optical, and chemical analyses, we propose and validate a hypothesis to explain the doping mechanism. Doping is ascribed to donor states in the band gap of Al_xO_y, which donate electrons or not, based on the alignment of the electronic bands of the 2D TMDC. Through systematic experimental characterization, incorporation of impurities (e.g., carbon) is identified as the likely cause of such states. By modulating the carbon concentration in the capping oxide, doping can be controlled. Through systematic and comprehensive experimental analysis, this study correlates, for the first time, 2D TMDC doping to the carbon incorporation on dielectric encapsulation layers. We highlight the possibility to engineer dopant layers to control the material selectivity and doping concentration in 2D TMDC.

Two-Dimensional Materials in Biosensing and Healthcare: From In Vitro Diagnostics to Optogenetics and Beyond

Since the isolation of graphene in 2004, there has been an exponentially growing number of reports on layered two-dimensional (2D) materials for applications ranging from protective coatings to biochemical sensing. Due to the exceptional, and often tunable, electrical, optical, electrochemical, and physical properties of these materials, they can serve as the active sensing element or a supporting substrate for diverse healthcare applications. In this review, we provide a survey of the recent reports on the applications of 2D materials in biosensing and other emerging healthcare areas, ranging from wearable technologies to optogenetics to neural interfacing. Specifically, this review provides (i) a holistic evaluation of relevant material properties across a wide range of 2D systems, (ii) a comparison of 2D material-based biosensors to the state-of-the-art, (iii) relevant material synthesis approaches specifically reported for healthcare applications, and (iv) the technological considerations to facilitate mass production and commercialization.

Sono-Assisted Surface Energy Driven Assembly of 2D Materials on Flexible Polymer Substrates: A Green Assembly Method Using Water

The challenges in achieving a green and scalable integration of two-dimensional (2D) materials with flexible polymer substrates present a major barrier for the application of 2D materials, such as graphene, MoS₂, and h-BN for flexible devices. Here, we create a sono-assisted surface energy driven assembly (SASEDA) method that can achieve foot-scale to micrometer-scale assembly of 2D materials, form a conductive network in as short as 10 s, and build hierarchical and hybrid flexible devices such as sensors, resistors, and capacitors by using water as the dispersion solvent. SASEDA highlights two counterintuitive innovations. First, we use an "unfavorable" solvent (i.e., water) for both 2D materials (e.g., graphene, MoS₂, and h-BN) and polymer substrates (e.g., polydimethylsiloxane) to drive the assembly process. Second, we use a weak sono-field (0.3 W/cm²) generated by a regular sonication bath cleaner to enhance the assembly efficiency and reorganize and unify the assembly network. This method and its principle pave the way toward affordable large-scale 2D material-based flexible devices.

Continuously Tuning Electronic Properties of Few-Layer Molybdenum Ditelluride with in Situ Aluminum Modification toward Ultrahigh Gain Complementary Inverters

Semiconducting molybdenum ditelluride (2H-MoTe₂), a two-dimensional (2D) transition metal dichalcogenide, has attracted extensive research attention due to its favorable physical properties for future electronic devices, such as appropriate bandgap, ambipolar transport characteristic, and good chemical stability. The rational tuning of its electronic properties is a key point to achieve MoTe₂-based complementary electronic and optoelectronic devices. Herein, we demonstrate the dynamic and effective control of the electronic properties of few-layer MoTe₂, through the in situ surface modification with aluminum (Al) adatoms, with a view toward high-performance complementary inverter devices. MoTe₂ is found to be significantly electron doped by Al, exhibiting a continuous transport transition from p-dominated ambipolar to n-type unipolar with enhanced electron mobility. Using a spatially controlled Al doping technique, both p- and n-channels are established on a single MoTe₂ nanosheet, which gives complementary inverters with a record-high gain of ∼195, which stands out in the 2D family of materials due to the balanced p- and n-transport in Al-modified MoTe₂. Our studies coupled with the tunable nature of in situ modification enable MoTe₂ to be a promising candidate for high-performance complementary electronics.

Controllable P- and N-Type Conversion of MoTe2 via Oxide Interfacial Layer for Logic Circuits

To realize basic electronic units such as complementary metal-oxide-semiconductor (CMOS) inverters and other logic circuits, the selective and controllable fabrication of p- and n-type transistors with a low Schottky barrier height is highly desirable. Herein, an efficient and nondestructive technique of electron-charge transfer doping by depositing a thin Al₂ O₃ layer on chemical vapor deposition (CVD)-grown 2H-MoTe₂ is utilized to tune the doping from p- to n-type. Moreover, a type-controllable MoTe₂ transistor with a low Schottky barrier height is prepared. The selectively converted n-type MoTe₂ transistor from the p-channel exhibits a maximum on-state current of 10 µA, with a higher electron mobility of 8.9 cm² V^-1 s^-1 at a drain voltage (V_ds ) of 1 V with a low Schottky barrier height of 28.4 meV. To validate the aforementioned approach, a prototype homogeneous CMOS inverter is fabricated on a CVD-grown 2H-MoTe₂ single crystal. The proposed inverter exhibits a high DC voltage gain of 9.2 with good dynamic behavior up to a modulation frequency of 1 kHz. The proposed approach may have potential for realizing future 2D transition metal dichalcogenide-based efficient and ultrafast electronic units with high-density circuit components under a low-dimensional regime.

Small footprint transistor architecture for photoswitching logic and in situ memory

The need for continuous size downscaling of silicon transistors is driving the industrial development of strategies to enable further footprint reduction^1,2. The atomic thickness of two-dimensional materials allows the potential realization of high-area-efficiency transistor architectures. However, until now, the design of devices composed of two-dimensional materials has mimicked the basic architecture of silicon circuits^3-6. Here, we report a transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell. Unlike the conventional transistor working mechanism, the two-dimensional material logic transistor has two surface channels. Furthermore, the material thickness can change the logic behaviour-the architecture can be flexibly expanded to achieve in situ memory such as logic computing and data storage convergence in the same device. These devices are potentially promising candidates for the construction of new chips that can perform computing and storage with high area-efficiency and unique functions.

Symmetric Ultrafast Writing and Erasing Speeds in Quasi-Nonvolatile Memory via van der Waals Heterostructures

Due to the large gap in timescale between volatile memory and nonvolatile memory technologies, quasi-nonvolatile memory based on 2D materials has become a viable technology for filling the gap. By exploiting the elaborate energy band structure of 2D materials, a quasi-nonvolatile memory with symmetric ultrafast write-1 and erase-0 speeds and long refresh time is reported. Featuring the 2D semifloating gate architecture, an extrinsic p-n junction is used to charge or discharge the floating gate. Owing to the direct injection or recombination of charges from the floating gate electrode, the erasing speed is greatly enhanced to nanosecond timescale. Combined with the ultrafast write-1 speed, symmetric ultrafast operations on the nanosecond timescale are achieved, which are ≈10⁶ times faster than other memories based on 2D materials. In addition, the refresh time after a write-1 operation is 219 times longer than that of dynamic random access memory. This performance suggests that quasi-nonvolatile memory has great potential to decrease power consumption originating from frequent refresh operations, and usher in the next generation of high-speed and low-power memory technology.

Threshold Voltage Control of Multilayered MoS2 Field-Effect Transistors via Octadecyltrichlorosilane and their Applications to Active Matrixed Quantum Dot Displays Driven by Enhancement-Mode Logic Gates

In recent past, for next-generation device opportunities such as sub-10 nm channel field-effect transistors (FETs), tunneling FETs, and high-end display backplanes, tremendous research on multilayered molybdenum disulfide (MoS₂ ) among transition metal dichalcogenides has been actively performed. However, nonavailability on a matured threshold voltage control scheme, like a substitutional doping in Si technology, has been plagued for the prosperity of 2D materials in electronics. Herein, an adjustment scheme for threshold voltage of MoS₂ FETs by using self-assembled monolayer treatment via octadecyltrichlorosilane is proposed and demonstrated to show MoS₂ FETs in an enhancement mode with preservation of electrical parameters such as field-effect mobility, subthreshold swing, and current on-off ratio. Furthermore, the mechanisms for threshold voltage adjustment are systematically studied by using atomic force microscopy, Raman, temperature-dependent electrical characterization, etc. For validation of effects of threshold voltage engineering on MoS₂ FETs, full swing inverters, comprising enhancement mode drivers and depletion mode loads are perfectly demonstrated with a maximum gain of 18.2 and a noise margin of ≈45% of 1/2 V_DD . More impressively, quantum dot light-emitting diodes, driven by enhancement mode MoS₂ FETs, stably demonstrate 120 cd m^-2 at the gate-to-source voltage of 5 V, exhibiting promising opportunities for future display application.

Optimized single-layer MoS2 field-effect transistors by non-covalent functionalisation

Field-effect transistors (FETs) with non-covalently functionalised molybdenum disulfide (MoS2) channels grown by chemical vapour deposition (CVD) on SiO2 are reported. The dangling-bond-free surface of MoS2 was functionalised with a perylene bisimide derivative to allow for the deposition of Al2O3 dielectric. This allowed the fabrication of top-gated, fully encapsulated MoS2 FETs. Furthermore, by the definition of vertical contacts on MoS2, devices, in which the channel area was never exposed to polymers, were fabricated. The MoS2 FETs showed some of the highest mobilities for transistors fabricated on SiO2 with Al2O3 as the top-gate dielectric reported so far. Thus, gate-stack engineering using innovative chemistry is a promising approach for the fabrication of reliable electronic devices based on 2D materials.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 10⁶ times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.