A Fully Integrated Wireless Compressed Sensing Neural Signal Acquisition System for Chronic Recording and Brain Machine Interface

Implementation of Sound Direction Detection and Mixed Source Separation in Embedded Systems

In recent years, embedded system technologies and products for sensor networks and wearable devices used for monitoring people's activities and health have become the focus of the global IT industry. In order to enhance the speech recognition capabilities of wearable devices, this article discusses the implementation of audio positioning and enhancement in embedded systems using embedded algorithms for direction detection and mixed source separation. The two algorithms are implemented using different embedded systems: direction detection developed using TI TMS320C6713 DSK and mixed source separation developed using Raspberry Pi 2. For mixed source separation, in the first experiment, the average signal-to-interference ratio (SIR) at 1 m and 2 m distances was 16.72 and 15.76, respectively. In the second experiment, when evaluated using speech recognition, the algorithm improved speech recognition accuracy to 95%.

Efficient in Vivo Neural Signal Compression Using an Autoencoder-Based Neural Network

Conventional in vivo neural signal processing involves extracting spiking activity within the recorded signals from an ensemble of neurons and transmitting only spike counts over an adequate interval. However, for brain-computer interface (BCI) applications utilizing continuous local field potentials (LFPs) for cognitive decoding, the volume of neural data to be transmitted to a computer imposes relatively high data rate requirements. This is particularly true for BCIs employing high-density intracortical recordings with hundreds or thousands of electrodes. This article introduces the first autoencoder-based compression digital circuit for the efficient transmission of LFP neural signals. Various algorithmic and architectural-level optimizations are implemented to significantly reduce the computational complexity and memory requirements of the designed in vivo compression circuit. This circuit employs an autoencoder-based neural network, providing a robust signal reconstruction. The application-specific integrated circuit (ASIC) of the in vivo compression logic occupies the smallest silicon area and consumes the lowest power among the reported state-of-the-art compression ASICs. Additionally, it offers a higher compression rate and a superior signal-to-noise and distortion ratio.

A Portable and a Scalable Multi-Channel Wireless Recording System for Wearable Electromyometrial Imaging

Electromyometrial imaging (EMMI) technology has emerged as one of the promising technology that can be used for non-invasive pregnancy risk stratification and for preventing complications due to pre-term birth. Current EMMI systems are bulky and require a tethered connection to desktop instrumentation, as a result, the system cannot be used in non-clinical and ambulatory settings. In this article, we propose an approach for designing a scalable, portable wireless EMMI recording system that can be used for in-home and remote monitoring. The wearable system uses a non-equilibrium differential electrode multiplexing approach to enhance signal acquisition bandwidth and to reduce the artifacts due to electrode drifts, amplifier 1/f noise, and bio-potential amplifier saturation. A combination of active shielding, a passive filter network, and a high-end instrumentation amplifier ensures sufficient input dynamic range ([Formula: see text]) such that the system can simultaneously acquire different bio-potential signals like maternal electrocardiogram (ECG) in addition to the EMMI electromyogram (EMG) signals. We show that the switching artifacts and the channel cross-talk introduced due to non-equilibrium sampling can be reduced using a compensation technique. This enables the system to be potentially scaled to a large number of channels without significantly increasing the system power dissipation. We demonstrate the feasibility of the proposed approach in a clinical setting using an 8-channel battery-powered prototype which dissipates less than 8 μW per channel for a signal bandwidth of 1 KHz.

Design and Optimization of Planar Spiral Coils for Powering Implantable Neural Recording Microsystem

This paper presents a design and optimization method utilizing inductive coupling coils for wireless power transfer in implantable neural recording microsystems, aiming at maximizing power transfer efficiency, which is essential for reducing externally transmitted power and ensuring biological tissue safety. The modeling of inductive coupling is simplified by combining semi-empirical formulations with theoretical models. By introducing the optimal resonant load transformation, the coil optimization is decoupled from an actual load impedance. The complete design optimization process of the coil parameters is given, which takes the maximum theoretical power transfer efficiency as the objective function. When the actual load changes, only the load transformation network needs to be updated instead of rerunning the entire optimization process. Planar spiral coils are designed to power neural recording implants given the challenges of limited implantable space, stringent low-profile restrictions, high-power transmission requirements and biocompatibility. The modeling calculation, electromagnetic simulation and measurement results are compared. The operating frequency of the designed inductive coupling is 13.56 MHz, the outer diameter of the implanted coil is 10 mm and the working distance between the external coil and the implanted coil is 10 mm. The measured power transfer efficiency is 70%, which is close to the maximum theoretical transfer efficiency of 71.9%, confirming the effectiveness of this method.

The next generation of hybrid microfluidic/integrated circuit chips: recent and upcoming advances in high-speed, high-throughput, and multifunctional lab-on-IC systems

Since the field's inception, pioneers in microfluidics have made significant progress towards realizing complete lab-on-chip systems capable of sophisticated sample analysis and processing. One avenue towards this goal has been to join forces with the related field of microelectronics, using integrated circuits (ICs) to perform on-chip actuation and sensing. While early demonstrations focused on using microfluidic-IC hybrid chips to miniaturize benchtop instruments, steady advancements in the field have enabled a new generation of devices that expand past miniaturization into high-performance applications that would not be possible without IC hybrid integration. In this review, we identify recent examples of labs-on-chip that use high-resolution, high-speed, and multifunctional electronic and photonic chips to expand the capabilities of conventional sample analysis. We focus on three particularly active areas: a) high-throughput integrated flow cytometers; b) large-scale microelectrode arrays for stimulation and multimodal sensing of cells over a wide field of view; c) high-speed biosensors for studying molecules with high temporal resolution. We also discuss recent advancements in IC technology, including on-chip data processing techniques and lens-free optics based on integrated photonics, that are poised to further advance microfluidic-IC hybrid chips.

An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive Δ - Δ Σ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 μ W , and an input-referred noise of 7.7 ± 0.4 μ V rms in the AP band and 11.9 ± 1.1 μ V rms in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

A 21.3%-Efficiency Clipped-Sinusoid UWB Impulse Radio Transmitter With Simultaneous Inductive Powering and Data Receiving

An ultra-wide-band impulse-radio (UWB-IR) transmitter (TX) for low-energy biomedical microsystems is presented. High power efficiency is achieved by modulating an LC tank that always resonates in the steady state during transmission. A new clipped-sinusoid scheme is proposed for on-off keying (OOK)-modulation, which is implemented by a voltage clipper circuit with on-chip biasing generation. The TX is designed to provide a high data-rate wireless link within the 3-5 GHz band. The chip was fabricated in 130 nm CMOS technology and fully characterized. State-of-the-art power efficiency of 21.3% was achieved at a data-rate of 230 Mbps and energy consumption of 21pJ/b. A bit-error-rate (BER) of less than 10 ^-6 was measured at a distance of 1 m without pulse averaging. In addition, simultaneous wireless powering and VCO-based data transmission are supported. A potential extension to a VCO-free all-wireless mode to further reduce the power consumption is also discussed.

A 0.43 g Wireless Battery-Less Neural Recorder With On-Chip Microelectrode Array and Integrated Flexible Antenna

This work presents a single-chip battery-less neural recorder with 12 on-die microelectrodes. It can be powered wirelessly up to 16 cm away from a horn antenna at 915 MHz and only consumes 104 μW dc power for accessing 10 enabled recording sites simultaneously, transmitting at 5 Mbps. The implantable device integrated with a flexible antenna weighs only 0.43 gram. In vivo measurements on an unrestricted mouse have been successfully conducted, showing response to visual stimuli.

Low-Power Lossless Data Compression for Wireless Brain Electrophysiology

Wireless electrophysiology opens important possibilities for neuroscience, especially for recording brain activity in more natural contexts, where exploration and interaction are not restricted by the usual tethered devices. The limiting factor is transmission power and, by extension, battery life required for acquiring large amounts of neural electrophysiological data. We present a digital compression algorithm capable of reducing electrophysiological data to less than 65.5% of its original size without distorting the signals, which we tested in vivo in experimental animals. The algorithm is based on a combination of delta compression and Huffman codes with optimizations for neural signals, which allow it to run in small, low-power Field-Programmable Gate Arrays (FPGAs), requiring few hardware resources. With this algorithm, a hardware prototype was created for wireless data transmission using commercially available devices. The power required by the algorithm itself was less than 3 mW, negligible compared to the power saved by reducing the transmission bandwidth requirements. The compression algorithm and its implementation were designed to be device-agnostic. These developments can be used to create a variety of wired and wireless neural electrophysiology acquisition systems with low power and space requirements without the need for complex or expensive specialized hardware.

A Vector Quantization-Based Spike Compression Approach Dedicated to Multichannel Neural Recording Microsystems

Implantable high-density multichannel neural recording microsystems provide simultaneous recording of brain activities. Wireless transmission of the entire recorded data causes high bandwidth usage, which is not tolerable for implantable applications. As a result, a hardware-friendly compression module is required to reduce the amount of data before it is transmitted. This paper presents a novel compression approach that utilizes a spike extractor and a vector quantization (VQ)-based spike compressor. In this approach, extracted spikes are vector quantized using an unsupervised learning process providing a high spike compression ratio (CR) of 10-80. A combination of extracting and compressing neural spikes results in a significant data reduction as well as preserving the spike waveshapes. The compression performance of the proposed approach was evaluated under variant conditions. We also developed new architectures such that the hardware blocks of our approach can be implemented more efficiently. The compression module was implemented in a 180-nm standard CMOS process achieving a SNDR of 14.49[Formula: see text]dB and a classification accuracy (CA) of 99.62% at a CR of 20, while consuming 4[Formula: see text][Formula: see text]W power and 0.16[Formula: see text]mm² chip area per channel.

Multi-Channel Biopotential Acquisition System Using Frequency-Division Multiplexing With Cable Motion Artifact Suppression

A multi-channel, CMOS-based biopotential acquisition system is presented that uses amplitude modulated, frequency division multiplexing (AM-FDM) to decrease wire count and provide resilience against motion artifacts and cable noise. Differential active electrode (AE) pairs capture surface biopotential signals, each modulated by a different carrier frequency and combined via current-domain summing. The presented approach requires only a single wire for signal transmission between AEs and back-end readout, along with clock and ground wires, to support multiple active electrodes using a 3-wire cable. Frequency modulation prior to transmission mitigates the effect of low-frequency cable motion artifacts and 50/60 Hz mains interference in the cable. A prototype FDM-based biopotential acquisition system was implemented in a 180 nm CMOS process, including a four-channel front-end active electrode IC for signal conditioning and modulation, and a back-end IC for demodulation and digitization. Each channel occupies 0.75 mm [Formula: see text] and consumes 43.8 μ W, inclusive of ADC power. Using both AE and BE ICs, a four-channel biopotential recording system is demonstrated using a 3-wire interface, where the system achieves attenuation of low-frequency cable motion artifacts by 15X and 60 Hz mains noise coupled into the cable by 62X.

A System-on-Chip for Closed-loop Optogenetic Sleep Modulation

Stimulation of target neuronal populations using optogenetic techniques during specific sleep stages has begun to elucidate the mechanisms and effects of sleep. To conduct closed-loop optogenetic sleep studies in untethered animals, we designed a fully integrated, low-power system-on-chip (SoC) for real-time sleep stage classification and stage-specific optical stimulation. The SoC consists of a 4-channel analog front-end for recording polysomnography signals, a mixed-signal machine-learning (ML) core, and a 16-channel optical stimulation back-end. A novel ML algorithm and innovative circuit design techniques improved the online classification performance while minimizing power consumption. The SoC was designed and simulated in 180 nm CMOS technology. In an evaluation using an expert labeled sleep database with 20 subjects, the SoC achieves a high sensitivity of 0.806 and a specificity of 0.947 in discriminating 5 sleep stages. Overall power consumption in continuous operation is 97 µW.

Compressed Sensing of Extracellular Neurophysiology Signals: A Review

This article presents a comprehensive survey of literature on the compressed sensing (CS) of neurophysiology signals. CS is a promising technique to achieve high-fidelity, low-rate, and hardware-efficient neural signal compression tasks for wireless streaming of massively parallel neural recording channels in next-generation neural interface technologies. The main objective is to provide a timely retrospective on applying the CS theory to the extracellular brain signals in the past decade. We will present a comprehensive review on the CS-based neural recording system architecture, the CS encoder hardware exploration and implementation, the sparse representation of neural signals, and the signal reconstruction algorithms. Deep learning-based CS methods are also discussed and compared with the traditional CS-based approaches. We will also extend our discussion to cover the technical challenges and prospects in this emerging field.

Recording Strategies for High Channel Count, Densely Spaced Microelectrode Arrays

Neuroscience research into how complex brain functions are implemented at an extra-cellular level requires in vivo neural recording interfaces, including microelectrodes and read-out circuitry, with increased observability and spatial resolution. The trend in neural recording interfaces toward employing high-channel-count probes or 2D microelectrodes arrays with densely spaced recording sites for recording large neuronal populations makes it harder to save on resources. The low-noise, low-power requirement specifications of the analog front-end usually requires large silicon occupation, making the problem even more challenging. One common approach to alleviating this consumption area burden relies on time-division multiplexing techniques in which read-out electronics are shared, either partially or totally, between channels while preserving the spatial and temporal resolution of the recordings. In this approach, shared elements have to operate over a shorter time slot per channel and active area is thus traded off against larger operating frequencies and signal bandwidths. As a result, power consumption is only mildly affected, although other performance metrics such as in-band noise or crosstalk may be degraded, particularly if the whole read-out circuit is multiplexed at the analog front-end input. In this article, we review the different implementation alternatives reported for time-division multiplexing neural recording systems, analyze their advantages and drawbacks, and suggest strategies for improving performance.

Electro-Quasistatic Animal Body Communication for Untethered Rodent Biopotential Recording

Continuous multi-channel monitoring of biopotential signals is vital in understanding the body as a whole, facilitating accurate models and predictions in neural research. The current state of the art in wireless technologies for untethered biopotential recordings rely on radiative electromagnetic (EM) fields. In such transmissions, only a small fraction of this energy is received since the EM fields are widely radiated resulting in lossy inefficient systems. Using the body as a communication medium (similar to a 'wire') allows for the containment of the energy within the body, yielding order(s) of magnitude lower energy than radiative EM communication. In this work, we introduce Animal Body Communication (ABC), which utilizes the concept of using the body as a medium into the domain of untethered animal biopotential recording. This work, for the first time, develops the theory and models for animal body communication circuitry and channel loss. Using this theoretical model, a sub-inch[Formula: see text] [1″ × 1″ × 0.4″], custom-designed sensor node is built using off the shelf components which is capable of sensing and transmitting biopotential signals, through the body of the rat at significantly lower powers compared to traditional wireless transmissions. In-vivo experimental analysis proves that ABC successfully transmits acquired electrocardiogram (EKG) signals through the body with correlation [Formula: see text] when compared to traditional wireless communication modalities, with a 50[Formula: see text] reduction in power consumption.

Electrophysiology Read-Out Tools for Brain-on-Chip Biotechnology

Brain-on-Chip (BoC) biotechnology is emerging as a promising tool for biomedical and pharmaceutical research applied to the neurosciences. At the convergence between lab-on-chip and cell biology, BoC couples in vitro three-dimensional brain-like systems to an engineered microfluidics platform designed to provide an in vivo-like extrinsic microenvironment with the aim of replicating tissue- or organ-level physiological functions. BoC therefore offers the advantage of an in vitro reproduction of brain structures that is more faithful to the native correlate than what is obtained with conventional cell culture techniques. As brain function ultimately results in the generation of electrical signals, electrophysiology techniques are paramount for studying brain activity in health and disease. However, as BoC is still in its infancy, the availability of combined BoC-electrophysiology platforms is still limited. Here, we summarize the available biological substrates for BoC, starting with a historical perspective. We then describe the available tools enabling BoC electrophysiology studies, detailing their fabrication process and technical features, along with their advantages and limitations. We discuss the current and future applications of BoC electrophysiology, also expanding to complementary approaches. We conclude with an evaluation of the potential translational applications and prospective technology developments.

Neural signal analysis with memristor arrays towards high-efficiency brain-machine interfaces

Brain-machine interfaces are promising tools to restore lost motor functions and probe brain functional mechanisms. As the number of recording electrodes has been exponentially rising, the signal processing capability of brain–machine interfaces is falling behind. One of the key bottlenecks is that they adopt conventional von Neumann architecture with digital computation that is fundamentally different from the working principle of human brain. In this work, we present a memristor-based neural signal analysis system, where the bio-plausible characteristics of memristors are utilized to analyze signals in the analog domain with high efficiency. As a proof-of-concept demonstration, memristor arrays are used to implement the filtering and identification of epilepsy-related neural signals, achieving a high accuracy of 93.46%. Remarkably, our memristor-based system shows nearly 400× improvements in the power efficiency compared to state-of-the-art complementary metal-oxide-semiconductor systems. This work demonstrates the feasibility of using memristors for high-performance neural signal analysis in next-generation brain–machine interfaces.

Designing energy efficient and high performance brain-machine interfaces with millions of recording electrodes for in-situ analysis remains a challenge. Here, the authors develop a memristor-based neural signal analysis system capable of filtering and identifying epilepsy-related brain activities with an accuracy of 93.46%.

Power Efficiency Comparison of Event-Driven and Fixed-Rate Signal Conversion and Compression for Biomedical Applications

Energy-constrained biomedical recording systems need power-efficient data converters and good signal compression in order to meet the stringent power consumption requirements of many applications. In literature today, typically a SAR ADC in combination with digital compression is used. Recently, alternative event-driven sampling techniques have been proposed that incorporate compression in the ADC, such as level-crossing A/D conversion. This paper describes the power efficiency analysis of such level-crossing ADC (LCADC) and the traditional fixed-rate SAR ADC with simple compression. A model for the power consumption of the LCADC is derived, which is then compared to the power consumption of the SAR ADC with zero-order hold (ZOH) compression for multiple biosignals (ECG, EMG, EEG, and EAP). The LCADC is more power efficient than the SAR ADC up to a cross-over point in quantizer resolution (for example 8 bits for an EEG signal). This cross-over point decreases with the ratio of the maximum to average slope in the signal of the application. It also changes with the technology and design techniques used. The LCADC is thus suited for low to medium resolution applications. In addition, the event-driven operation of an LCADC results in fewer data to be transmitted in a system application. The event-driven LCADC without timer and with single-bit quantizer achieves a reduction in power consumption at system level of two orders of magnitude, an order of magnitude better than the SAR ADC with ZOH compression. At system level, the LCADC thus offers a big advantage over the SAR ADC.

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, low-power Delta-Sigma analog-to-digital converter (ADC) and a real-time spike processor based on one exponential component-polynomial component (EC-PC) algorithm. High-precision data conversion with low power consumption and small chip area is achieved by employing several techniques, such as opamp-sharing, multi-bit successive approximation (SAR) quantizer, two-step summation, and ultra-low distortion data weighted averaging (DWA). The on-chip EC-PC engine enables low latency, automatic detection, and extraction of spiking activities, thus supporting closed-loop control, real-time data compression and /or neural information decoding. The prototype chip was fabricated in a 0.13  μm CMOS process and verified in both bench-top and In-Vivo experiments. Bench-top measurement results indicate the designed ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 91.8 dB and a dynamic range of 93.0 dB over a 10 kHz bandwidth, where the total power consumption of the modulator is only 20  μW at 1.0 V supply, corresponding to a figure-of-merit (FOM) of 31.4fJ /conversion-step. In In-Vivo experiments, the proposed DAQ system has been demonstrated to obtain high-quality neural activities from a rat's motor cortex and also greatly reduce recovery time from system saturation due to electrical microstimulation.

Multi-Channel Neural Recording Implants: A Review

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain-machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

Analysis of the capacitance of minimally insulated parallel wires implanted in biological tissue

State of the art bioelectronic implants are using thin cables for therapeutic electrical stimulation. If cable insulation is thin, biological tissue surrounding cables can be unintentionally stimulated. The capacitance of the cable must be much less than the stimulating electrodes to ensure stimulating currents are delivered to the electrode-tissue interface. This work derives and experimentally validates a model to determine the capacitance of parallel cables implanted in biological tissue. Biological tissue has a high relative permittivity, so the capacitance of cabling implanted in the human body depends on cable insulation thickness. Simulations and measurements demonstrate that insulation thickness influences the capacitance of implanted parallel cables across almost two orders of magnitude: from 20 pF/m to 700 pF/m. The results are verified using four different methods: solving the Laplacian numerically from first principles, using a commercially available electrostatic solver, and measuring twelve different parallel pairs of wires using two different potentiostats. Cable capacitance simulations and measurements are performed in air, a porcine blood pool and porcine muscle tissue. The results do not differ by more than 30% for a given cable across simulation and measurement methodologies. The modelling in this work can be used to design cabling for minimally-invasive biomedical implants.

A Software-Defined Radio Receiver for Wireless Recording From Freely Behaving Animals

To eliminate tethering effects on the small animals' behavior during electrophysiology experiments, such as neural interfacing, a robust and wideband wireless data link is needed for communicating with the implanted sensing elements without blind spots. We present a software-defined radio (SDR) based scalable data acquisition system, which can be programmed to provide coverage over standard-sized or customized experimental arenas. The incoming RF signal with the highest power among SDRs is selected in real-time to prevent data loss in the presence of spatial and angular misalignments between the transmitter (Tx) and receiver (Rx) antennas. A 32-channel wireless neural recording system-on-a-chip (SoC), known as WINeRS-8, is embedded in a headstage and transmits digitalized raw neural signals, which are sampled at 25 kHz/ch, at 9 Mbps via on-off keying (OOK) of a 434 MHz RF carrier. Measurement results show that the dual-SDR Rx system reduces the packet loss down to 0.12%, on average, by eliminating the blind spots caused by the moving Tx directionality. The system operation is verified in vivo on a freely behaving rat and compared with a commercial hardwired system.

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

Large-scale in vivo electrophysiology requires tools that enable simultaneous recording of multiple brain regions at single-neuron level. This calls for the design of more compact neural probes that offer even larger arrays of addressable sites and high channel counts. With this aim, we present in this paper a quad-shank approach to integrate as many as 5,120 sites on a single probe. Compact fully-differential recording channels were designed using a single-gain-stage neural amplifier with a 14-bit ADC, achieving a mean input-referred noise of 7.44 μV_rms in the action-potential band and 7.65 μV_rms in the local-field-potential band, a mean total harmonic distortion of 0.17% at 1 kHz and a mean input-referred offset of 169 μV. The probe base incorporates 384 channels with on-chip power management, reference-voltage generation and digital control, thus achieving the highest level of integration in a neural probe and excellent channel-to-channel uniformity. Therefore, no calibration or external circuitry are required to achieve the above-mentioned performance. With a total area of 2.2 × 8.67 mm² and a power consumption of 36.5 mW, the presented probe enables full-system miniaturization for acute or chronic use in small rodents.

A 3 mm × 3 mm Fully Integrated Wireless Power Receiver and Neural Interface System-on-Chip

A miniaturized, fully integrated wireless power receiver system-on-chip with embedded 16-channel electrode array and data transceiver for electrocortical neural recording and stimulation is presented. An H-tree power and signal distribution network throughout the SoC maintains high quality factor up to 11 in the on-chip receiver coil at 144 MHz resonant frequency while rejecting RF interference in sensitive neural interface circuits owing to its perpendicular and equidistant geometry. A multi-mode buck-boost resonant regulating rectifier (B ²R ³) offers greater than 11-dB input dynamic range in RF reception and less than 1 mV overshoot in transient load regulation. At 10 mm link distance, the 9 mm ² neural interface SoC fabricated in a 180 nm silicon-on-insulator (SOI) process attains an overall wireless power transmission system efficiency (WSE) of 3.4% in driving a 160  μW load yielding a WSE figure-of-merit of 131, while maintaining signal integrity in analog recording and wireless data transmission that comprise the on-chip load.

A Real-Time Spike Sorting System Using Parallel OSort Clustering

This article presents an efficient design and implementation of a real-time spike sorting system using unsupervised clustering. We utilize the online sorting (OSort) algorithm and model it first in both floating-point and fixed-point numerical representations to accurately assess the feasibility of our hardware architecture and also reliably analyze the sorting accuracy. For efficient hardware realization of OSort, we propose a modified parallel OSort algorithm. By reducing the number of required memory accesses, the number of computations performed for the management and upkeep of cluster averages and cluster merging is substantially reduced. By limiting the number of supported clusters per channel, the classification/clustering latency is significantly reduced compared to the previously published work, making the designed OSort system applicable for in-vivo spike sorting. The proposed OSort hardware architecture utilizes a novel memory configuration scheme to parallelize the OSort algorithm, which allows us to avoid using relatively large memory queues for storing detected spike waveforms and process them concurrently to the spike cluster management. The characteristics and implementation results of the designed OSort-based spike sorting system on a Xilinx Artix-7 field-programmable gate array (FPGA) are presented. The ASIC implementation of the designed system is estimated to occupy 2.57 mm² in a standard 32-nm CMOS process. Post-layout power estimation shows that the ASIC will dissipate 2.78 mW, while operating at 24 kHz.

Frameworks for Efficient Brain-Computer Interfacing

One challenge present in brain-computer interface (BCI) circuits is finding a balance between real-time on-chip processing in-vivo and wireless transmission of neural signals for off-chip in-silico processing. This article presents three potential frameworks for investigating an area- and energy-efficient realization of BCI circuits. The first framework performs spike detection on the filtered neural signal on a brain-implantable chip and only transmits detected spikes wirelessly for offline classification and decoding. The second framework performs in-vivo compression of the on-chip detected spikes prior to wireless transmission for substantially reducing wireless transmission overhead. The third framework performs spike sorting in-vivo on the brain-implantable chip to classify detected spikes on-chip and hence, even further reducing wireless data transmission rate at the expense of more signal processing. To alleviate the on-chip computation of spike sorting and also utilizing a more area- and energy-effective design, this work employs, for the first time, to the best of our knowledge, an artificial neural network (ANN) instead of using relatively computationally-intensive conventional spike sorting algorithms. The ASIC implementation results of the designed frameworks are presented and their feasibility for efficient in-vivo processing of neural signals is discussed. Compared to the previously-published BCI systems, the presented frameworks reduce the area and power consumption of implantable circuits.

Future of Neural Interfaces

The technological ability to capture electrophysiological activity of populations of cortical neurons through chronic implantable devices has led to significant advancements in the field of brain-computer interfaces. Recent progress in the field has been driven by developments in integrated microelectronics, wireless communications, materials science, and computational neuroscience. Here, we review major device development landmarks in the arena of neural interfaces from FDA-approved clinical systems to prototype head-mounted and fully implantable wireless systems for multi-channel neural recording. Additionally, we provide an outlook toward next-generation, highly miniaturized technologies for minimally invasive, vastly parallel neural interfaces for naturalistic, closed-loop neuroprostheses.

Human motor decoding from neural signals: a review

Many people suffer from movement disability due to amputation or neurological diseases. Fortunately, with modern neurotechnology now it is possible to intercept motor control signals at various points along the neural transduction pathway and use that to drive external devices for communication or control. Here we will review the latest developments in human motor decoding. We reviewed the various strategies to decode motor intention from human and their respective advantages and challenges. Neural control signals can be intercepted at various points in the neural signal transduction pathway, including the brain (electroencephalography, electrocorticography, intracortical recordings), the nerves (peripheral nerve recordings) and the muscles (electromyography). We systematically discussed the sites of signal acquisition, available neural features, signal processing techniques and decoding algorithms in each of these potential interception points. Examples of applications and the current state-of-the-art performance were also reviewed. Although great strides have been made in human motor decoding, we are still far away from achieving naturalistic and dexterous control like our native limbs. Concerted efforts from material scientists, electrical engineers, and healthcare professionals are needed to further advance the field and make the technology widely available in clinical use.

Compact and Low-Power Neural Spike Compression Using Undercomplete Autoencoders

Implantable microsystems that collect and transmit neural data are becoming very useful entities in the field of neuroscience. Limited by high data rates, on-chip compression is often required to transmit the recorded data without causing power dissipation at levels that would damage sensitive brain tissue. This paper presents a data compression system designed for brain-computer interfaces (BCIs) based on undercomplete autoencoders. To the best of our knowledge, the proposed system is the first to achieve an average spike reconstruction quality of 14-dB signal-to-noise-and-distortion ratio (SNDR) at a 32× compression ratio (CR), 18-dB SNDR at a 16× CR, 22-dB SNDR at an 8× CR, and 35-dB SNDR at a 4× CR of neural spikes. The spike detection and autoencoder-based compression modules are designed and implemented in a standard 45-nm CMOS process. The post-synthesis simulation results report that the compression module consumes between 1.4 and 222.5 [Formula: see text] of power per channel and takes between 0.018 and 0.082mm² of silicon area, depending on the desired CR and number of channels.

An Unsupervised Compressed Sensing Algorithm for Multi-Channel Neural Recording and Spike Sorting

We propose an unsupervised compressed sensing (CS)-based framework to compress, recover, and cluster neural action potentials. This framework can be easily integrated into high-density multi-electrode neural recording VLSI systems. Embedding spectral clustering and group structures in dictionary learning, we extend the proposed framework to unsupervised spike sorting without prior label information. Additionally, we incorporate group sparsity concepts in the dictionary learning to enable the framework for multi-channel neural recordings, as in tetrodes. To further improve spike sorting success rates in the CS framework, we embed template matching in sparse coding to jointly predict clusters of spikes. Our experimental results demonstrate that the proposed CS-based framework can achieve a high compression ratio (8:1 to 20:1), with a high quality reconstruction performance (>8 dB) and a high spike sorting accuracy (>90%).

An Inductively-Powered Wireless Neural Recording and Stimulation System for Freely-Behaving Animals

An inductively-powered wireless integrated neural recording and stimulation (WINeRS-8) system-on-a-chip (SoC) that is compatible with the EnerCage-HC2 for wireless/battery-less operation has been presented for neuroscience experiments on freely behaving animals. WINeRS-8 includes a 32-ch recording analog front end, a 4-ch current-controlled stimulator, and a 434 MHz on - off keying data link to an external software- defined radio wideband receiver (Rx). The headstage also has a bluetooth low energy link for controlling the SoC. WINeRS-8/EnerCage-HC2 systems form a bidirectional wireless and battery-less neural interface within a standard homecage, which can support longitudinal experiments in an enriched environment. Both systems were verified in vivo on rat animal model, and the recorded signals were compared with hardwired and battery-powered recording results. Realtime stimulation and recording verified the system's potential for bidirectional neural interfacing within the homecage, while continuously delivering 35 mW to the hybrid WINeRS-8 headstage over an unlimited period.

Neurophysiological Evaluation of a Customizable μECoG-based Wireless Brain Implant

The number of implantable bidirectional neural interfaces available for neuroscientific research applications is still limited, despite the rapidly increasing number of customized components. We previously reported on how to translate available components into "ready-to-use" wireless implantable systems utilizing components off-the-shelf (COTS). The aim of the present study was to verify the viability of a micro-electrocorticographic ($\mu $ECoG) device built by this approach. Functionality for both neural recording and stimulation was evaluated in an ovine animal model using acoustic stimuli and cortical electrical stimulation, respectively. We show that auditory evoked responses were reliably recorded in both time and frequency domain and present data that demonstrates the cortical electrical stimulation functionality. The successful recording of neuronal activity suggests that the device can compete with existing implantable systems as a neurotechnological research tool.

Multimed: An Integrated, Multi-Application Platform for the Real-Time Recording and Sub-Millisecond Processing of Biosignals

Enhanced understanding and control of electrophysiology mechanisms are increasingly being hailed as key knowledge in the fields of modern biology and medicine. As more and more excitable cell mechanics are being investigated and exploited, the need for flexible electrophysiology setups becomes apparent. With that aim, we designed Multimed, which is a versatile hardware platform for the real-time recording and processing of biosignals. Digital processing in Multimed is an arrangement of generic processing units from a custom library. These can freely be rearranged to match the needs of the application. Embedded onto a Field Programmable Gate Array (FPGA), these modules utilize full-hardware signal processing to lower processing latency. It achieves constant latency, and sub-millisecond processing and decision-making on 64 channels. The FPGA core processing unit makes Multimed suitable as either a reconfigurable electrophysiology system or a prototyping platform for VLSI implantable medical devices. It is specifically designed for open- and closed-loop experiments and provides consistent feedback rules, well within biological microseconds timeframes. This paper presents the specifications and architecture of the Multimed system, then details the biosignal processing algorithms and their digital implementation. Finally, three applications utilizing Multimed in neuroscience and diabetes research are described. They demonstrate the system’s configurability, its multi-channel, real-time processing, and its feedback control capabilities.

Continuous-Time Acquisition of Biosignals Using a Charge-Based ADC Topology

This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of 5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35  CMOS technology occupying a compact footprint of 0.12 mm². Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75  W from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.

An Implantable Peripheral Nerve Recording and Stimulation System for Experiments on Freely Moving Animal Subjects

A new study with rat sciatic nerve model for peripheral nerve interfacing is presented using a fully-implanted inductively-powered recording and stimulation system in a wirelessly-powered standard homecage that allows animal subjects move freely within the homecage. The Wireless Implantable Neural Recording and Stimulation (WINeRS) system offers 32-channel peripheral nerve recording and 4-channel current-controlled stimulation capabilities in a 3 × 1.5 × 0.5 cm³ package. A bi-directional data link is established by on-off keying pulse-position modulation (OOK-PPM) in near field for narrow-band downlink and 433 MHz OOK for wideband uplink. An external wideband receiver is designed by adopting a commercial software defined radio (SDR) for a robust wideband data acquisition on a PC. The WINeRS-8 prototypes in two forms of battery-powered headstage and wirelessly-powered implant are validated in vivo, and compared with a commercial system. In the animal study, evoked compound action potentials were recorded to verify the stimulation and recording capabilities of the WINeRS-8 system with 32-ch penetrating and 4-ch cuff electrodes on the sciatic nerve of awake freely-behaving rats. Compared to the conventional battery-powered system, WINeRS can be used in closed-loop recording and stimulation experiments over extended periods without adding the burden of carrying batteries on the animal subject or interrupting the experiment.

A Low-Power Current-Reuse Analog Front-End for High-Density Neural Recording Implants

Studying brain activity in vivo requires collecting bioelectrical signals from several microelectrodes simultaneously in order to capture neuron interactions. In this work, we present a new current-reuse analog front-end (AFE), which is scalable to very large numbers of recording channels, thanks to its small implementation silicon area and its low-power consumption. This current-reuse AFE, which is including a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), employs a new fully differential current-mirror topology using fewer transistors, and improving several design parameters, such as power consumption and noise, over previous current-reuse amplifier circuit implementations. We show that the proposed current-reuse amplifier can provide a theoretical noise efficiency factor (NEF) as low as 1.01, which is the lowest reported theoretical NEF provided by an LNA topology. A foue-channel current-reuse AFE implemented in a CMOS 0.18-μm technology is presented as a proof-of-concept. T-network capacitive circuits are used to decrease the size of input capacitors and to increase the gain accuracy in the AFE. The measured performance of the whole AFE is presented. The total power consumption per channel, including the LNA and the PGA stage, is 9 μW (4.5 μW for LNA and 4.5 μW for PGA), for an input referred noise of 3.2 μV_rms, achieving a measured NEF of 1.94. The entire AFE presents three selectable gains of 35.04, 43.1, and 49.5 dB, and occupies a die area of 0.072 mm² per channel. The implemented circuit has a measured inter-channel rejection ratio of 54 dB. In vivo recording results obtained with the proposed AFE are reported. It successfully allows collecting low-amplitude extracellular action potential signals from a tungsten wire microelectrode implanted in the hippocampus of a laboratory mouse.

Simultaneous Multimodal PC Access for People With Disabilities by Integrating Head Tracking, Speech Recognition, and Tongue Motion

Multimodal Tongue Drive System (mTDS) is a highly integrated wireless assistive technology (AT) in the form of a lightweight wearable headset that utilizes three remaining key control and communication abilities in people with severe physical disabilities, such as tetraplegia, to provide them with effective access to computers: 1) tongue motion for discrete/switch-based control (e.g., clicking), 2) head tracking for proportional control (e.g., mouse pointer movements), and 3) speech recognition for typing, all available simultaneously. The mTDS architecture is presented here with new sensor signal processing algorithm for head tracking. To evaluate the device performance, it was compared against keyboard-and-mouse (KnM) combination, the gold standard in computer input methods, by 15 able-bodied participants, who used both mTDS and KnM to generate and sent an email with randomly selected content, under a 5-minute time constraint. In four repetitions, in the last trial, it took participants only 1.8 times longer to complete the email task, on average, using the mTDS versus KnM at 82.4% typing accuracy. Mean task completion time and typing accuracy improved 24.6% and 18.8% from first to fourth trial using mTDS. Multimodal simultaneous discrete and proportional control input options of mTDS, plus rapid typing, is expected to provide more effective computer access to people with severe physical disabilities.

A Time-Domain Analog Spatial Compressed Sensing Encoder for Multi-Channel Neural Recording

A time-domain analog spatial compressed sensing encoder for neural recording applications is proposed. Owing to the advantage of MEMS technologies, the number of channels on a silicon neural probe array has doubled in 7.4 years, and therefore, a greater number of recording channels and higher density of front-end circuitry is required. Since neural signals such as action potential (AP) have wider signal bandwidth than that of an image sensor, a data compression technique is essentially required for arrayed neural recording systems. In this paper, compressed sensing (CS) is employed for data reduction, and a novel time-domain analog CS encoder is proposed. A simpler and lower power circuit than conventional analog or digital CS encoders can be realized by using the proposed CS encoder. A prototype of the proposed encoder was fabricated in a 180 nm 1P6M CMOS process, and it achieved an active area of 0.0342 mm 2 / ch . and an energy efficiency of 25.0 pJ / ch . · conv .

A 64-Channel Versatile Neural Recording SoC With Activity-Dependent Data Throughput

Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low-noise (2.1 V), low-power (23  W per analogue channel) neural recording system-on-chip (SoC). This features individually configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth, and sampling rate settings can be independently configured to extract local field potentials at a low data-rate and/or action potentials (APs) at a higher data rate. The sampled data are streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve 2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting coprocessor to provide a real-time (low latency) output. The system has been implemented in a commercially available 0.35-m CMOS technology occupying a silicon area of 19.1 mm (0.3 mm gross per channel), demonstrating a low-power and efficient architecture that could be further optimized by aggressive technology and supply voltage scaling.

Energy Analysis of Decoders for Rakeness-Based Compressed Sensing of ECG Signals

In recent years, compressed sensing (CS) has proved to be effective in lowering the power consumption of sensing nodes in biomedical signal processing devices. This is due to the fact the CS is capable of reducing the amount of data to be transmitted to ensure correct reconstruction of the acquired waveforms. Rakeness-based CS has been introduced to further reduce the amount of transmitted data by exploiting the uneven distribution to the sensed signal energy. Yet, so far no thorough analysis exists on the impact of its adoption on CS decoder performance. The latter point is of great importance, since body-area sensor network architectures may include intermediate gateway nodes that receive and reconstruct signals to provide local services before relaying data to a remote server. In this paper, we fill this gap by showing that rakeness-based design also improves reconstruction performance. We quantify these findings in the case of ECG signals and when a variety of reconstruction algorithms are used either in a low-power microcontroller or a heterogeneous mobile computing platform.

Event-driven processing for hardware-efficient neural spike sorting

OBJECTIVE

The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing.

APPROACH

(1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability.

MAIN RESULTS

It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources.

SIGNIFICANCE

By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.