Quantum Confinement Effect in Amorphous In-Ga-Zn-O Heterojunction Channels for Thin-Film Transistors

Solution-processed bilayer InGaZnO/In2O3thin film transistors at low temperature by lightwave annealing

At low temperatures about 230 °C, bilayer InGaZnO/In2O3thin film transistors (TFTs) were prepared by a solution process with lightwave annealing. The InGaZnO/In2O3bilayer TFTs with SiO2as dielectric layer show high electrical performances, such as a mobility of 7.63 cm2V-1s-1, a threshold voltage (Vth) of 3.8 V, and an on/off ratio higher than 107, which are superior to single-layer InGaZnO TFTs or In2O3TFTs. Moreover, bilayer InGaZnO/In2O3TFTs demonstrated a great bias stability enhancement due to the introduction of top InGaZnO film act as a passivation layer, which could prevent the interaction of ambient air with the bottom In2O3layer. By using high dielectric constant AlOxfilm, the InGaZnO/In2O3TFTs exhibit an improved mobility of 47.7 cm2V-1s-1. The excellent electrical performance of the solution-based InGaZnO/In2O3TFTs shows great application potential for low-cost flexible printed electronics.

Metal-Oxide Heterojunction: From Material Process to Neuromorphic Applications

As technologies like the Internet, artificial intelligence, and big data evolve at a rapid pace, computer architecture is transitioning from compute-intensive to memory-intensive. However, traditional von Neumann architectures encounter bottlenecks in addressing modern computational challenges. The emulation of the behaviors of a synapse at the device level by ionic/electronic devices has shown promising potential in future neural-inspired and compact artificial intelligence systems. To address these issues, this review thoroughly investigates the recent progress in metal-oxide heterostructures for neuromorphic applications. These heterostructures not only offer low power consumption and high stability but also possess optimized electrical characteristics via interface engineering. The paper first outlines various synthesis methods for metal oxides and then summarizes the neuromorphic devices using these materials and their heterostructures. More importantly, we review the emerging multifunctional applications, including neuromorphic vision, touch, and pain systems. Finally, we summarize the future prospects of neuromorphic devices with metal-oxide heterostructures and list the current challenges while offering potential solutions. This review provides insights into the design and construction of metal-oxide devices and their applications for neuromorphic systems.

Achieving High Performance of ZnSnO Thin-Film Transistor via Homojunction Strategy

The zinc-tin-oxide (ZTO) thin-film transistor (TFT) is one of the most promising candidates for advanced display applications, though its popularity is limited by its performances. In this work, a heterojunction channel strategy was adopted to regulate the electron transport behaviors and the TFT performances by manipulating the concentration and the distribution of oxygen vacancies, and a reasonable physical model was proposed based on experimental and simulation results. It is difficult to mediate the contradiction between mobility and threshold voltage for the single channel. Via a heterojunction channel strategy, desirable TFT performances, with mobility of 12.5 cm2/Vs, threshold voltage of 1.2 V and Ion/Ioff of 3 × 109, are achieved when the oxygen-vacancy-enriched layer gets close to the gate insulator (GI). The enhanced performances can be mainly attributed to the formation of two-dimensional electron gas (2DEG), the insensitive potential barrier and the reasonable distribution of oxygen vacancy. On the contrary, when the oxygen-vacancy-enriched layer stays away from GI, all the main performances degenerate due to the vulnerable potential well. The findings may facilitate the development and application of heterojunction channels for improving the performances of electronic devices.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In-Ga-Zn-O bilayer channel configuration

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In-Ga-Zn-O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 10⁹), low SS value (180 mV dec^-1), and high current drivability (13.6μAμm^-1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm^-1for 10⁴s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.