Distinctive in-Plane Cleavage Behaviors of Two-Dimensional Layered Materials

Mechanical exfoliation from bulk layered crystal is widely used for preparing two-dimensional (2D) layered materials, which involves not only out-of-plane interlayer cleavage but also in-plane fracture. Through a statistical analysis on the exfoliated 2D flakes, we reveal the in-plane cleavage behaviors of six representative layered materials, including graphene, h-BN, 2H phase MoS2, 1T phase PtS2, FePS3, and black phosphorus. In addition to the well-known interlayer cleavage, these 2D layered materials show a distinctive tendency to fracture along certain in-plane crystallography orientations. With theoretical modeling and analysis, these distinct in-plane cleavage behaviors can be understood as a result of the competition between the release of the elastic energy and the increase of the surface energy during the fracture process. More importantly, these in-plane cleavage behaviors provide a fast and noninvasive method using optical microscopy to identify the lattice direction of mechanical exfoliated 2D layered materials.

High Current Density and Low Thermal Conductivity of Atomically Thin Semimetallic WTe2

Two-dimensional (2D) semimetals beyond graphene have been relatively unexplored in the atomically thin limit. Here, we introduce a facile growth mechanism for semimetallic WTe2 crystals and then fabricate few-layer test structures while carefully avoiding degradation from exposure to air. Low-field electrical measurements of 80 nm to 2 μm long devices allow us to separate intrinsic and contact resistance, revealing metallic response in the thinnest encapsulated and stable WTe2 devices studied to date (3-20 layers thick). High-field electrical measurements and electrothermal modeling demonstrate that ultrathin WTe2 can carry remarkably high current density (approaching 50 MA/cm(2), higher than most common interconnect metals) despite a very low thermal conductivity (of the order ∼3 Wm(-1) K(-1)). These results suggest several pathways for air-stable technological viability of this layered semimetal.

Picosecond Electric-Field-Induced Threshold Switching in Phase-Change Materials

Many chalcogenide glasses undergo a breakdown in electronic resistance above a critical field strength. Known as threshold switching, this mechanism enables field-induced crystallization in emerging phase-change memory. Purely electronic as well as crystal nucleation assisted models have been employed to explain the electronic breakdown. Here, picosecond electric pulses are used to excite amorphous Ag_{4}In_{3}Sb_{67}Te_{26}. Field-dependent reversible changes in conductivity and pulse-driven crystallization are observed. The present results show that threshold switching can take place within the electric pulse on subpicosecond time scales-faster than crystals can nucleate. This supports purely electronic models of threshold switching and reveals potential applications as an ultrafast electronic switch.

Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array

Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

High-Performance p-Type Black Phosphorus Transistor with Scandium Contact

A record high current density of 580 μA/μm is achieved for long-channel, few-layer black phosphorus transistors with scandium contacts after 400 K vacuum annealing. The annealing effectively improves the on-state current and Ion/Ioff ratio by 1 order of magnitude and the subthreshold swing by ∼2.5×, whereas Al2O3 capping significantly degrades transistor performances, resulting in 5× lower on-state current and 3× lower Ion/Ioff ratio. The influences of moisture on black phosphorus metal contacts are elucidated by analyzing the hysteresis of 3-20 nm thick black phosphorus transistors with scandium and gold contacts under different conditions: as-fabricated, after vacuum annealing, and after Al2O3 capping. The optimal black phosphorus film thickness for transistors with scandium contacts is found to be ∼10 nm. Moreover, p-type performance is shown in all transistors with scandium contacts, suggesting that the Fermi level is pinned closer to the valence band regardless of the flake thickness.

Statistical Study on the Schottky Barrier Reduction of Tunneling Contacts to CVD Synthesized MoS2

Creating high-quality, low-resistance contacts is essential for the development of electronic applications using two-dimensional (2D) layered materials. Many previously reported methods for lowering the contact resistance rely on volatile chemistry that either oxidize or degrade in ambient air. Nearly all reported efforts have been conducted on only a few devices with mechanically exfoliated flakes which is not amenable to large scale manufacturing. In this work, Schottky barrier heights of metal-MoS2 contacts to devices fabricated from CVD synthesized MoS2 films were reduced by inserting a thin tunneling Ta2O5 layer between MoS2 and metal contacts. Schottky barrier height reductions directly correlate with exponential reductions in contact resistance. Over two hundred devices were tested and contact resistances extracted for large scale statistical analysis. As compared to metal-MoS2 Schottky contacts without an insulator layer, the specific contact resistivity has been lowered by up to 3 orders of magnitude and current values increased by 2 orders of magnitude over large area (>4 cm(2)) films.

In Situ Tuning of Switching Window in a Gate-Controlled Bilayer Graphene-Electrode Resistive Memory Device

A resistive random access memory (RRAM) device with a tunable switching window is demonstrated for the first time. The SET voltage can be continuously tuned from 0.27 to 4.5 V by electrical gating from -10 to +35 V. The gate-controlled bilayer graphene-electrode RRAM can function as 1D1R and potentially increase the RRAM density.

Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier

Phase-change memory (PCM) is an important class of data storage, yet lowering the programming current of individual devices is known to be a significant challenge. Here we improve the energy-efficiency of PCM by placing a graphene layer at the interface between the phase-change material, Ge2Sb2Te5 (GST), and the bottom electrode (W) heater. Graphene-PCM (G-PCM) devices have ∼40% lower RESET current compared to control devices without the graphene. This is attributed to the graphene as an added interfacial thermal resistance which helps confine the generated heat inside the active PCM volume. The G-PCM achieves programming up to 10(5) cycles, and the graphene could further enhance the PCM endurance by limiting atomic migration or material segregation at the bottom electrode interface.

Metal oxide-resistive memory using graphene-edge electrodes

The emerging paradigm of ‘abundant-data' computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors. Todays computing technology, however, cannot scale to satisfy such big data applications with the required throughput and energy efficiency. The next technology frontier will be monolithically integrated chips with three-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene edge to assemble a resistive memory (∼3 Å thick) stacked in a vertical three-dimensional structure. We report some of the lowest power and energy consumption among the emerging non-volatile memories due to an extremely thin electrode with unique properties, low programming voltages, and low current. Circuit analysis of the three-dimensional architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

Increasing memory performance and density will require new breakthroughs in atomic-scale technology and three-dimensional device architectures. Here, the authors demonstrate a memory just 3 Å thick that can be stacked by exploiting the atomically thin edge of monolayer graphene.

Large-area assembly of densely aligned single-walled carbon nanotubes using solution shearing and their application to field-effect transistors

Dense alignment of single-walled carbon nanotubes over a large area is demonstrated using a novel solution-shearing technique. A density of 150-200 single-walled carbon nanotubes per micro-meter is achieved with a current density of 10.08 μA μm(-1) at VDS = -1 V. The on-current density is improved by a factor of 45 over that of random-network single-walled carbon nanotubes.

A general design strategy for block copolymer directed self-assembly patterning of integrated circuits contact holes using an alphabet approach

Directed self-assembly (DSA) is a promising lithography candidate for technology nodes beyond 14 nm. Researchers have shown contact hole patterning for random logic circuits using DSA with small physical templates. This paper introduces an alphabet approach that uses a minimal set of small physical templates to pattern all contacts configurations on integrated circuits. We illustrate, through experiments, a general and scalable template design strategy that links the DSA material properties to the technology node requirements.

Continuous wireless pressure monitoring and mapping with ultra-small passive sensors for health monitoring and critical care

Continuous monitoring of internal physiological parameters is essential for critical care patients, but currently can only be practically achieved via tethered solutions. Here we report a wireless, real-time pressure monitoring system with passive, flexible, millimetre-scale sensors, scaled down to unprecedented dimensions of 1 × 1 × 0.1 cubic millimeters. This level of dimensional scaling is enabled by novel sensor design and detection schemes, which overcome the operating frequency limits of traditional strategies and exhibit insensitivity to lossy tissue environments. We demonstrate the use of this system to capture human pulse waveforms wirelessly in real time as well as to monitor in vivo intracranial pressure continuously in proof-of-concept mice studies using sensors down to 2.5 × 2.5 × 0.1 cubic millimeters. We further introduce printable wireless sensor arrays and show their use in real-time spatial pressure mapping. Looking forward, this technology has broader applications in continuous wireless monitoring of multiple physiological parameters for biomedical research and patient care.

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance.

Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems

Neuromorphic computing is an attractive computation paradigm that complements the von Neumann architecture. The salient features of neuromorphic computing are massive parallelism, adaptivity to the complex input information, and tolerance to errors. As one of the most crucial components in a neuromorphic system, the electronic synapse requires high device integration density and low-energy consumption. Oxide-based resistive switching devices have been shown to be a promising candidate to realize the functions of the synapse. However, the intrinsic variation increases significantly with the reduced spike energy due to the reduced number of oxygen vacancies in the conductive filament region. The large resistance variation may degrade the accuracy of neuromorphic computation. In this work, we develop an oxide-based electronic synapse to suppress the degradation caused by the intrinsic resistance variation. The synapse utilizes a three-dimensional vertical structure including several parallel oxide-based resistive switching devices on the same nanopillar. The fabricated three-dimensional electronic synapse exhibits the potential for low fabrication cost, high integration density, and excellent performances, such as low training energy per spike, gradual resistance transition under identical pulse training scheme, and good repeatability. A pattern recognition computation is simulated based on a well-known neuromorphic visual system to quantify the feasibility of the three-dimensional vertical structured synapse for the application of neuromorphic computation systems. The simulation results show significantly improved recognition accuracy from 65 to 90% after introducing the three-dimensional synapses.

Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology

Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications.

Ultrafast characterization of phase-change material crystallization properties in the melt-quenched amorphous phase

Phase change materials are widely considered for application in nonvolatile memories because of their ability to achieve phase transformation in the nanosecond time scale. However, the knowledge of fast crystallization dynamics in these materials is limited because of the lack of fast and accurate temperature control methods. In this work, we have developed an experimental methodology that enables ultrafast characterization of phase-change dynamics on a more technologically relevant melt-quenched amorphous phase using practical device structures. We have extracted the crystallization growth velocity (U) in a functional capped phase change memory (PCM) device over 8 orders of magnitude (10(-10) < U < 10(-1) m/s) spanning a wide temperature range (415 < T < 580 K). We also observed direct evidence of non-Arrhenius crystallization behavior in programmed PCM devices at very high heating rates (>10(8) K/s), which reveals the extreme fragility of Ge2Sb2Te5 in its supercooled liquid phase. Furthermore, these crystallization properties were studied as a function of device programming cycles, and the results show degradation in the cell retention properties due to elemental segregation. The above experiments are enabled by the use of an on-chip fast heater and thermometer called as microthermal stage (MTS) integrated with a vertical phase change memory (PCM) cell. The temperature at the PCM layer can be controlled up to 600 K using MTS and with a thermal time constant of 800 ns, leading to heating rates ∼10(8) K/s that are close to the typical device operating conditions during PCM programming. The MTS allows us to independently control the electrical and thermal aspects of phase transformation (inseparable in a conventional PCM cell) and extract the temperature dependence of key material properties in real PCM devices.

Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations

Precise electrical manipulation of nanoscale defects such as vacancy nano-filaments is highly desired for the multi-level control of ReRAM. In this paper we present a systematic investigation on the pulse-train operation scheme for reliable multi-level control of conductive filament evolution. By applying the pulse-train scheme to a 3 bit per cell HfO2 ReRAM, the relative standard deviations of resistance levels are improved up to 80% compared to the single-pulse scheme. The observed exponential relationship between the saturated resistance and the pulse amplitude provides evidence for the gap-formation model of the filament-rupture process.

Carbon nanotube circuit integration up to sub-20 nm channel lengths

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

VLSI-compatible carbon nanotube doping technique with low work-function metal oxides

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.

Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory

The vertical scaling for the multi-layer stacked 3D vertical resistive random access memory (RRAM) cross-point array is investigated. The thickness of the multi-layer stack for a 3D RRAM is a key factor for determining the storage density. A vertical RRAM cell with plane electrode thickness (tm) scaled down to 5 nm, aiming to minimize 3D stack height, is experimentally demonstrated. An improvement factor of 5 in device density can be achieved as compared to a previous demonstration using a 22 nm thick plane electrode. It is projected that 37 layers can be stacked for a lithographic half-pitch (F) = 26 nm and total thickness of one stack (T) = 21 nm, delivering a bit density of 72.8 nm(2)/cell.

Stochastic learning in oxide binary synaptic device for neuromorphic computing

Hardware implementation of neuromorphic computing is attractive as a computing paradigm beyond the conventional digital computing. In this work, we show that the SET (off-to-on) transition of metal oxide resistive switching memory becomes probabilistic under a weak programming condition. The switching variability of the binary synaptic device implements a stochastic learning rule. Such stochastic SET transition was statistically measured and modeled for a simulation of a winner-take-all network for competitive learning. The simulation illustrates that with such stochastic learning, the orientation classification function of input patterns can be effectively realized. The system performance metrics were compared between the conventional approach using the analog synapse and the approach in this work that employs the binary synapse utilizing the stochastic learning. The feasibility of using binary synapse in the neurormorphic computing may relax the constraints to engineer continuous multilevel intermediate states and widens the material choice for the synaptic device design.

Synaptic electronics: materials, devices and applications

In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing. Performance metrics desirable for large-scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented.

Atomic layer deposition of high-k dielectrics on single-walled carbon nanotubes: a Raman study

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, to realize a carbon nanotube field effect transistor (CNTFET) with excellent gate control, the high-k dielectrics between the CNT and the metal gate must have superb electrical properties and extremely high uniformity. Thus it is essential to understand the interactions between high-k materials and the SWCNTs to effectively control the transistor characteristics. In this study, we investigate the effects of atomic layer deposited (ALD) high-k dielectrics (Al2O3 and HfO2) on SWCNTs using Raman spectroscopy. We subjected the SWCNTs to various ALD cycles and studied the nucleation and growth of ALD dielectrics at defect sites using scanning electron microscopy and transmission electron microscopy images. We analyzed these samples using Raman spectroscopy and x-ray photoelectron spectroscopy. The Raman peak shifts of the G-peak and the 2D (G') peaks suggest doping and stress induced effects on the CNTs by the surrounding high-k oxide environment. Trends in the G-peak FWHM and G/D-peak ratios were identified and compared between Al2O3 and HfO2. We confirmed the ALD-deposited HfO2 is polycrystalline using x-ray diffraction and analyzed dielectric-CNT bonding states using XPS measurements. This study provides insights on the effects of ALD high-k materials on SWCNTs for future high-speed transistor applications.