Memory devices and applications for in-memory computing

Severity-Based Hierarchical ECG Classification Using Neural Networks

Timely detection of cardiac arrhythmia characterized by abnormal heartbeats can help in the early diagnosis and treatment of cardiovascular diseases. Wearable healthcare devices typically use neural networks to provide the most convenient way of continuously monitoring heart activity for arrhythmia detection. However, it is challenging to achieve high accuracy and energy efficiency in these smart wearable healthcare devices. In this work, we provide architecture-level solutions to deploy neural networks for cardiac arrhythmia classification. We have created a hierarchical structure after analyzing various neural network topologies where only required network components are activated to improve energy efficiency while maintaining high accuracy. In our proposed architecture, we introduce a severity-based classification approach to directly help the users of the wearable healthcare device as well as the medical professionals. Additionally, we have employed computation-in-memory based hardware to improve energy efficiency and area consumption by leveraging in-situ data processing and scalability of emerging memory technologies such as resistive random access memory (RRAM). Simulation experiments conducted using the MIT-BIH arrhythmia dataset show that the proposed architecture provides high accuracy while consuming average energy of 0.11 μJ per heartbeat classification and 0.11 mm² area, thereby achieving 25× improvement in average energy consumption and 12× improvement in area compared to the state-of-the-art.

Energy Efficient Neuro-Inspired Phase-Change Memory Based on Ge4 Sb6 Te7 as a Novel Epitaxial Nanocomposite

Phase-change memory (PCM) is a promising candidate for neuro-inspired, data-intensive artificial intelligence applications, which relies on the physical attributes of PCM materials including gradual change of resistance states and multilevel operation with low resistance drift. However, achieving these attributes simultaneously remains a fundamental challenge for PCM materials such as Ge₂ Sb₂ Te₅ , the most commonly used material. Here bi-directional gradual resistance changes with ≈10× resistance window using low energy pulses are demonstrated in nanoscale PCM devices based on Ge₄ Sb₆ Te₇ , a new phase-change nanocomposite material . These devices show 13 resistance levels with low resistance drift for the first 8 levels, a resistance on/off ratio of ≈1000, and low variability. These attributes are enabled by the unique microstructural and electro-thermal properties of Ge₄ Sb₆ Te₇ , a nanocomposite consisting of epitaxial SbTe nanoclusters within the Ge-Sb-Te matrix, and a higher crystallization but lower melting temperature than Ge₂ Sb₂ Te₅ . These results advance the pathway toward energy-efficient analog computing using PCM.

Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks

Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimensional ferroelectric NAND (3D FeNAND) array for the area-efficient hardware implementation of NNs. Vector-matrix multiplication is successfully demonstrated using the integrated 3D FeNAND arrays, and excellent pattern classification is achieved. By allocating each array of vertical layers in 3D FeNAND as the hidden layer of NN, each layer can be used to perform different tasks, and the classification of color-mixed patterns is achieved. This work provides a practical strategy to realize high-performance and highly efficient NN systems by stacking computation components vertically.

Low-Dimensional-Materials-Based Flexible Artificial Synapse: Materials, Devices, and Systems

With the rapid development of artificial intelligence and the Internet of Things, there is an explosion of available data for processing and analysis in any domain. However, signal processing efficiency is limited by the Von Neumann structure for the conventional computing system. Therefore, the design and construction of artificial synapse, which is the basic unit for the hardware-based neural network, by mimicking the structure and working mechanisms of biological synapses, have attracted a great amount of attention to overcome this limitation. In addition, a revolution in healthcare monitoring, neuro-prosthetics, and human-machine interfaces can be further realized with a flexible device integrating sensing, memory, and processing functions by emulating the bionic sensory and perceptual functions of neural systems. Until now, flexible artificial synapses and related neuromorphic systems, which are capable of responding to external environmental stimuli and processing signals efficiently, have been extensively studied from material-selection, structure-design, and system-integration perspectives. Moreover, low-dimensional materials, which show distinct electrical properties and excellent mechanical properties, have been extensively employed in the fabrication of flexible electronics. In this review, recent progress in flexible artificial synapses and neuromorphic systems based on low-dimensional materials is discussed. The potential and the challenges of the devices and systems in the application of neuromorphic computing and sensory systems are also explored.

An artificial synapse based on molecular junctions

Shrinking the size of the electronic synapse to molecular length-scale, for example, an artificial synapse directly fabricated by using individual or monolayer molecules, is important for maximizing the integration density, reducing the energy consumption, and enabling functionalities not easily achieved by other synaptic materials. Here, we show that the conductance of the self-assembled peptide molecule monolayer could be dynamically modulated by placing electrical biases, enabling us to implement basic synaptic functions. Both short-term plasticity (e.g., paired-pulse facilitation) and long-term plasticity (e.g., spike-timing-dependent plasticity) are demonstrated in a single molecular synapse. The dynamic current response is due to a combination of both chemical gating and coordination effects between Ag⁺ and hosting groups within peptides which adjusts the electron hopping rate through the molecular junction. In the end, based on the nonlinearity and short-term synaptic characteristics, the molecular synapses are utilized as reservoirs for waveform recognition with 100% accuracy at a small mask length.

Long-term memory and synapse-like dynamics in two-dimensional nanofluidic channels

Fine-tuned ion transport across nanoscale pores is key to many biological processes, including neurotransmission. Recent advances have enabled the confinement of water and ions to two dimensions, unveiling transport properties inaccessible at larger scales and triggering hopes of reproducing the ionic machinery of biological systems. Here we report experiments demonstrating the emergence of memory in the transport of aqueous electrolytes across (sub)nanoscale channels. We unveil two types of nanofluidic memristors depending on channel material and confinement, with memory ranging from minutes to hours. We explain how large time scales could emerge from interfacial processes such as ionic self-assembly or surface adsorption. Such behavior allowed us to implement Hebbian learning with nanofluidic systems. This result lays the foundation for biomimetic computations on aqueous electrolytic chips.

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-in-memory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal-ferroelectric-metal-insulator-semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal-oxide-semiconductor FET, leading to a large MW (∼11 V), fast operation speed (<20 ns), and high endurance (∼10¹¹ cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.

Optically Controllable Organic Logic-in-Memory: An Innovative Approach toward Ternary Data Processing and Storage

Logic-in-memory (LIM) has emerged as an energy-efficient computing technology, as it integrates logic and memory operations in a single device architecture. Herein, a concept of ternary LIM is established. First, a p-type 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) transistor is combined with an n-type PhC₂H₄-benzo[de]isoquinolino[1,8-gh]quinolone diimide (PhC2-BQQDI) transistor to obtain a binary memory inverter, in which a zinc phthalocyanine-cored polystyrene (ZnPc-PS₄) layer serves as a floating gate. The contrasting photoresponse of the transistors toward visible and ultraviolet light and the efficient hole-trapping ability of ZnPc-PS₄ enable us to achieve an optically controllable memory operation with a high memory window of 18 V. Then, a ternary memory inverter is developed using an anti-ambipolar transistor to achieve a three-level data processing and storage system for more advanced LIM applications. Finally, low-voltage operation of the devices is achieved by employing a high-k dielectric layer, which highlights the potential of the developed LIM units for next-generation low-power electronics.

Rational Design on Polymorphous Phase Switching in Molybdenum Diselenide-Based Memristor Assisted by All-Solid-State Reversible Intercalation toward Neuromorphic Application

In this work, a low-power memristor based on vertically stacked two-dimensional (2D) layered materials, achieved by plasma-assisted vapor reaction, as the switching material, with which the copper and gold metals as electrodes featured by reversible polymorphous phase changes from a conducting 1T-phase to a semiconducting 2H-one once copper cations interacted between vertical lamellar layers and vice versa, was demonstrated. Here, molybdenum diselenide was chosen as the switching material, and the reversible polymorphous phase changes activated by the intercalation of Cu cations were confirmed by pseudo-operando Raman scattering, transmission electron microscopy, and scanning photoelectron microscopy under high and low resistance states, respectively. The switching can be activated at about ±1 V with critical currents less than 10 μA with an on/off ratio approaching 100 after 100 cycles and low power consumption of ∼0.1 microwatt as well as linear weight updates controlled by the amount of intercalation. The work provides alternative feasibility of reversible and all-solid-state metal interactions, which benefits monolithic integrations of 2D materials into operative electronic circuits.

Humanlike spontaneous motion coordination of robotic fingers through spatial multi-input spike signal multiplexing

With advances in robotic technology, the complexity of control of robot has been increasing owing to fundamental signal bottlenecks and limited expressible logic state of the von Neumann architecture. Here, we demonstrate coordinated movement by a fully parallel-processable synaptic array with reduced control complexity. The synaptic array was fabricated by connecting eight ion-gel-based synaptic transistors to an ion gel dielectric. Parallel signal processing and multi-actuation control could be achieved by modulating the ionic movement. Through the integration of the synaptic array and a robotic hand, coordinated movement of the fingers was achieved with reduced control complexity by exploiting the advantages of parallel multiplexing and analog logic. The proposed synaptic control system provides considerable scope for the advancement of robotic control systems.

Colloquium: Advances in automation of quantum dot devices control

Arrays of quantum dots (QDs) are a promising candidate system to realize scalable, coupled qubit systems and serve as a fundamental building block for quantum computers. In such semiconductor quantum systems, devices now have tens of individual electrostatic and dynamical voltages that must be carefully set to localize the system into the single-electron regime and to realize good qubit operational performance. The mapping of requisite QD locations and charges to gate voltages presents a challenging classical control problem. With an increasing number of QD qubits, the relevant parameter space grows sufficiently to make heuristic control unfeasible. In recent years, there has been considerable effort to automate device control that combines script-based algorithms with machine learning (ML) techniques. In this Colloquium, a comprehensive overview of the recent progress in the automation of QD device control is presented, with a particular emphasis on silicon- and GaAs-based QDs formed in two-dimensional electron gases. Combining physics-based modeling with modern numerical optimization and ML has proven effective in yielding efficient, scalable control. Further integration of theoretical, computational, and experimental efforts with computer science and ML holds vast potential in advancing semiconductor and other platforms for quantum computing.

First Order Rate Law Analysis for Reset State in Vanadium Oxide Thin Film Resistive Random Access Memory Devices

In the reset state, the decay reaction mechanism and bipolar switching properties of vanadium oxide thin film RRAM devices for LRS/HRS are investigated and discussed here. To discover the properties of I-V switching curves, the first order rate law behaviors of the reset state between the resistant variety properties and the reaction time were observed. To verify the decay reaction mechanism in the reset state, vanadium oxide thin films from RRAM devices were measured by different constant voltage sampling and exhibited the same decay reaction rate constant. Finally, the electrical conduction transfer mechanism and metallic filament forming model described by I-V switching properties of the RRAM devices were proven and investigated.

3D-structured mesoporous silica memristors for neuromorphic switching and reservoir computing

Memristors are emerging as promising candidates for practical application in reservoir computing systems that are capable of temporal information processing. Here, we experimentally implement a physical reservoir computing system using resistive memristors based on three-dimensional (3D)-structured mesoporous silica (mSiO₂) thin films fabricated by a low cost, fast and vacuum-free sol-gel technique. The in situ learning capability and a classification accuracy of 100% on a standard machine learning dataset are experimentally demonstrated. The volatile (temporal) resistive switching in diffusive memristors arises from the formation and subsequent spontaneous rupture of conductive filaments via diffusion of Ag species within the 3D-structured nanopores of the mSiO₂ thin film. Besides volatile switching, the devices also exhibit a bipolar non-volatile resistive switching behavior when the devices are operated at a higher compliance current level. The implementation of mSiO₂ thin films opens the route to fabricate a simple and low cost dynamic memristor with a temporal information process functionality, which is essential for neuromorphic computing applications.

Ultrafast Near-Ideal Phase-Change Memristive Physical Unclonable Functions Driven by Amorphous State Variations

There is an ever-increasing demand for next-generation devices that do not require passwords and are impervious to cloning. For traditional hardware security solutions in edge computing devices, inherent limitations are addressed by physical unclonable functions (PUF). However, realizing efficient roots of trust for resource constrained hardware remains extremely challenging, despite excellent demonstrations with conventional silicon circuits and archetypal oxide memristor-based crossbars. An attractive, down-scalable approach to design efficient cryptographic hardware is to harness memristive materials with a large-degree-of-randomness in materials state variations, but this strategy is still not well understood. Here, the utilization of high-degree-of-randomness amorphous (A) state variations associated with different operating conditions via thermal fluctuation effects is demonstrated, as well as an integrated framework for in memory computing and next generation security primitives, viz., APUF, for achieving secure key generation and device authentication. Near ideal uniformity and uniqueness without additional initial writing overheads in weak memristive A-PUF is achieved. In-memory computing empowers a strong exclusive OR (XOR-) and-repeat A PUF construction to avoid machine learning attacks, while rapid crystallization processes enable large-sized-key reconfigurability. These findings pave the way for achieving a broadly applicable security primitive for enhancing antipiracy of integrated systems and product authentication in supply chains.

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. The different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

The Road for 2D Semiconductors in the Silicon Age

Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high-performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon-compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all-in-one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer-scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.

Integrated Memory Devices Based on 2D Materials

With the advent of the Internet of Things and big data, massive data must be rapidly processed and stored within a short timeframe. This imposes stringent requirements on memory hardware implementation in terms of operation speed, energy consumption, and integration density. To fulfill these demands, 2D materials, which are excellent electronic building blocks, provide numerous possibilities for developing advanced memory device arrays with high performance, smart computing architectures, and desirable downscaling. Over the past few years, 2D-material-based memory-device arrays with different working mechanisms, including defects, filaments, charges, ferroelectricity, and spins, have been increasingly developed. These arrays can be used to implement brain-inspired computing or sensing with extraordinary performance, architectures, and functionalities. Here, recent research into integrated, state-of-the-art memory devices made from 2D materials, as well as their implications for brain-inspired computing are surveyed. The existing challenges at the array level are discussed, and the scope for future research is presented.

Threshold Switching in Forming-Free Anodic Memristors Grown on Hf-Nb Combinatorial Thin-Film Alloys

The development of novel materials with coexisting volatile threshold and non-volatile memristive switching is crucial for neuromorphic applications. Hence, the aim of this work was to investigate the memristive properties of oxides in a Hf-Nb thin-film combinatorial system deposited by sputtering on Si substrates. The active layer was grown anodically on each Hf-Nb alloy from the library, whereas Pt electrodes were deposited as the top electrodes. The devices grown on Hf-45 at.% Nb alloys showed improved memristive performances reaching resistive state ratios up to a few orders of magnitude and achieving multi-level switching behavior while consuming low power in comparison with memristors grown on pure metals. The coexistence of threshold and resistive switching is dependent upon the current compliance regime applied during memristive studies. Such behaviors were explained by the structure of the mixed oxides investigated by TEM and XPS. The mixed oxides, with HfO₂ crystallites embedded in quasi amorphous and stoichiometrically non-uniform Nb oxide regions, were found to be favorable for the formation of conductive filaments as a necessary step toward memristive behavior. Finally, metal-insulator-metal structures grown on the respective alloys can be considered as relevant candidates for the future fabrication of anodic high-density in-memory computing systems for neuromorphic applications.

Silicon Wafer CMP Slurry Using a Hydrolysis Reaction Accelerator with an Amine Functional Group Remarkably Enhances Polishing Rate

Recently, as an alternative solution for overcoming the scaling-down limitations of logic devices with design length of less than 3 nm and enhancing DRAM operation performance, 3D heterogeneous packaging technology has been intensively researched, essentially requiring Si wafer polishing at a very high Si polishing rate (500 nm/min) by accelerating the degree of the hydrolysis reaction (i.e., Si-O-H) on the polished Si wafer surface during CMP. Unlike conventional hydrolysis reaction accelerators (i.e., sodium hydroxide and potassium hydroxide), a novel hydrolysis reaction accelerator with amine functional groups (i.e., 552.8 nm/min for ethylenediamine) surprisingly presented an Si wafer polishing rate >3 times higher than that of conventional hydrolysis reaction accelerators (177.1 nm/min for sodium hydroxide). This remarkable enhancement of the Si wafer polishing rate for ethylenediamine was principally the result of (i) the increased hydrolysis reaction, (ii) the enhanced degree of adsorption of the CMP slurry on the polished Si wafer surface during CMP, and (iii) the decreased electrostatic repulsive force between colloidal silica abrasives and the Si wafer surface. A higher ethylenediamine concentration in the Si wafer CMP slurry led to a higher extent of hydrolysis reaction and degree of adsorption for the slurry and a lower electrostatic repulsive force; thus, a higher ethylenediamine concentration resulted in a higher Si wafer polishing rate. With the aim of achieving further improvements to the Si wafer polishing rates using Si wafer CMP slurry including ethylenediamine, the Si wafer polishing rate increased remarkably and root-squarely with the increasing ethylenediamine concentration.

Ferroelectric Polarized in Transistor Channel Polarity Modulation for Reward-Modulated Spike-Time-Dependent Plasticity Application

Reward signals reflect the developmental tendency of reinforcement learning (RL) agents. Reward-modulated spike-time-dependent plasticity (R-STDP) is an efficient and concise information processing feature in RL. However, the physical construction of R-STDP normally demands complex circuit design engineering, resulting in large power consumption and large area. In this work, we studied the role of ferroelectric polarization in the modulation of carbon nanotube transistor channel polarity. Furthermore, we applied a modulating channel method to construct a 2T synaptic component by spin-coating technology. Based on the nonvolatility of ferroelectric polarization, the synaptic component constructed has the characteristics of reconfigurable polarity. One channel could be modulated to n-type and the other to p-type. One modulated channel was used to perform the STDP function when the reward signal arrived, and the other modulated channel was used to perform the anti-STDP function when the punishment signal arrived. Finally, R-STDP learning rules are implemented on hardware. This work provides a strategy for hardware construction of RL.

Highly Linear and Symmetric Synaptic Memtransistors Based on Polarization Switching in Two-Dimensional Ferroelectric Semiconductors

Brain-inspired neuromorphic computing hardware based on artificial synapses offers efficient solutions to perform computational tasks. However, the nonlinearity and asymmetry of synaptic weight updates in reported artificial synapses have impeded achieving high accuracy in neural networks. Here, this work develops a synaptic memtransistor based on polarization switching in a two-dimensional (2D) ferroelectric semiconductor (FES) of α-In₂ Se₃ for neuromorphic computing. The α-In₂ Se₃ memtransistor exhibits outstanding synaptic characteristics, including near-ideal linearity and symmetry and a large number of programmable conductance states, by taking the advantages of both memtransistor configuration and electrically configurable polarization states in the FES channel. As a result, the α-In₂ Se₃ memtransistor-type synapse reaches high accuracy of 97.76% for digit patterns recognition task in simulated artificial neural networks. This work opens new opportunities for using multiterminal FES memtransistors in advanced neuromorphic electronics.

Controlling the Formation of Conductive Pathways in Memristive Devices

Resistive random-access memories are promising candidates for novel computer architectures such as in-memory computing, multilevel data storage, and neuromorphics. Their working principle is based on electrically stimulated materials changes that allow access to two (digital), multiple (multilevel), or quasi-continuous (analog) resistive states. However, the stochastic nature of forming and switching the conductive pathway involves complex atomistic defect configurations resulting in considerable variability. This paper reveals that the intricate interplay of 0D and 2D defects can be engineered to achieve reproducible and controlled low-voltage formation of conducting filaments. The author find that the orientation of grain boundaries in polycrystalline HfO_x is directly related to the required forming voltage of the conducting filaments, unravelling a neglected origin of variability. Based on the realistic atomic structure of grain boundaries obtained from ultra-high resolution imaging combined with first-principles calculations including local strain, this paper shows how oxygen vacancy segregation energies and the associated electronic states in the vicinity of the Fermi level govern the formation of conductive pathways in memristive devices. These findings are applicable to non-amorphous valence change filamentary type memristive device. The results demonstrate that a fundamental atomistic understanding of defect chemistry is pivotal to design memristors as key element of future electronics.

Visible-Light-Stimulated Synaptic Phototransistors Based on CdSe Quantum Dot/In-Ga-Zn-O Hybrid Channels

Light-stimulated synaptic devices are promising candidates for the development of artificial intelligence systems because of their unique properties, which include broad bandwidths, low power consumption, and superior parallelism. The key to develop such devices is the realization of photoelectric synaptic behavior in them. In this work, visible-light-stimulated synaptic transistors based on CdSe quantum dot (CdSe QD)/amorphous In-Ga-Zn-O hybrid channels are proposed. This design can not only improve the charge separation efficiency of the photogenerated carriers, but also can induce delayed decay of the photocurrent. The improved charge separation efficiency enhances the photoelectric properties significantly, while the delayed decay of the photocurrent led to the realization of photoelectric synaptic behaviors. This simple and efficient method of fabricating light-stimulated phototransistors may inspire new research progress into the development of artificial intelligence systems.

Bayesian neural networks using magnetic tunnel junction-based probabilistic in-memory computing

Bayesian neural networks (BNNs) combine the generalizability of deep neural networks (DNNs) with a rigorous quantification of predictive uncertainty, which mitigates overfitting and makes them valuable for high-reliability or safety-critical applications. However, the probabilistic nature of BNNs makes them more computationally intensive on digital hardware and so far, less directly amenable to acceleration by analog in-memory computing as compared to DNNs. This work exploits a novel spintronic bit cell that efficiently and compactly implements Gaussian-distributed BNN values. Specifically, the bit cell combines a tunable stochastic magnetic tunnel junction (MTJ) encoding the trained standard deviation and a multi-bit domain-wall MTJ device independently encoding the trained mean. The two devices can be integrated within the same array, enabling highly efficient, fully analog, probabilistic matrix-vector multiplications. We use micromagnetics simulations as the basis of a system-level model of the spintronic BNN accelerator, demonstrating that our design yields accurate, well-calibrated uncertainty estimates for both classification and regression problems and matches software BNN performance. This result paves the way to spintronic in-memory computing systems implementing trusted neural networks at a modest energy budget.

Synergy of Spin-Orbit Torque and Built-In Field in Magnetic Tunnel Junctions with Tilted Magnetic Anisotropy: Toward Tunable and Reliable Spintronic Neurons

Owing to programmable nonlinear dynamics, magnetic domain wall (DW)-based devices can be configured to function as spintronic neurons, promising to execute sophisticated tasks as a human brain. Developing energy-efficient, CMOS compatible, reliable, and tunable spintronic neurons to emulate brain-inspired processes has been a key research goal for decades. Here, a new type of DW device is reported with biological neuron characteristics driven by the synergistic interaction between spin-orbit torque and built-in field (H_built-in ) in magnetic tunnel junctions, enabling time- and energy-efficient leaky-integrate-and-fire and self-reset neuromorphic implementations. A tilted magnetic anisotropic free layer is proposed and further executed to mitigate the DW retrograde motion by suppressing the Walker breakdown. Complementary experiments and micromagnetic co-simulation results show that the integrating/leaking time of the developed spintronic neuron can be tuned to 12/15 ns with an integrating power consumption of 65 µW, which is 36× and 1.84× time and energy efficient than the state-of-the-art alternatives, respectively. Moreover, the spatial distribution of H_built-in can be modulated by adjusting the width and compensation of the reference layer, facilitating tunable activation function generator exploration. Such architecture demonstrates great potential in both fundamental research and new trajectories of technology advancement for spintronic neuron hardware applications.

Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes

The deluge of sensors and data generating devices has driven a paradigm shift in modern computing from arithmetic-logic centric to data-centric processing. Data-centric processing require innovations at the device level to enable novel compute-in-memory (CIM) operations. A key challenge in the construction of CIM architectures is the conflicting trade-off between the performance and their flexibility for various essential data operations. Here, we present a transistor-free CIM architecture that permits storage, search, and neural network operations on sub-50 nm thick Aluminum Scandium Nitride ferroelectric diodes (FeDs). Our circuit designs and devices can be directly integrated on top of Silicon microprocessors in a scalable process. By leveraging the field-programmability, nonvolatility, and nonlinearity of FeDs, search operations are demonstrated with a cell footprint <0.12 μm² when projected onto 45 nm node technology. We further demonstrate neural network operations with 4-bit operation using FeDs. Our results highlight FeDs as candidates for efficient and multifunctional CIM platforms.

Ferroelectrics-Integrated Two-Dimensional Devices toward Next-Generation Electronics

Ferroelectric materials play an important role in a wide spectrum of semiconductor technologies and device applications. Two-dimensional (2D) van der Waals (vdW) ferroelectrics with surface-insensitive ferroelectricity that is significantly different from their traditional bulk counterparts have further inspired intensive interest. Integration of ferroelectrics into 2D-layered-material-based devices is expected to offer intriguing working principles and add desired functionalities for next-generation electronics. Herein, fundamental properties of ferroelectric materials that are compatible with 2D devices are introduced, followed by a critical review of recent advances on the integration of ferroelectrics into 2D devices. Representative device architectures and corresponding working mechanisms are discussed, such as ferroelectrics/2D semiconductor heterostructures, 2D ferroelectric tunnel junctions, and 2D ferroelectric diodes. By leveraging the favorable properties of ferroelectrics, a variety of functional 2D devices including ferroelectric-gated negative capacitance field-effect transistors, programmable devices, nonvolatile memories, and neuromorphic devices are highlighted, where the application of 2D vdW ferroelectrics is particularly emphasized. This review provides a comprehensive understanding of ferroelectrics-integrated 2D devices and discusses the challenges of applying them into commercial electronic circuits.

Physical Insights into Vacancy-Based Memtransistors: Toward Power Efficiency, Reliable Operation, and Scalability

Memtransistors that combine the properties of transistor and memristor hold significant promise for in-memory computing. While superior data storage capability is achieved in memtransistors through gate voltage-induced conductance modulation, the lateral device configuration would not only result in high write bias, which compromises the power efficiency, but also suffers from unsuccessful memory reset that leads to reliability concerns. To circumvent such performance limitations, an advanced physics-based model is required to uncover the dynamic resistive switching behavior and deduce the key driving parameters for the switching process. This work demonstrates a self-consistent physics-based model which incorporates the often-overlooked effects of lattice temperature, vacancy dynamics, and channel electrostatics to accurately solve the interaction between gate potential, ions, and carriers on the memristive switching mechanism. The completed model is carefully calibrated with an ambipolar WSe2 memtransistor and hence enables the investigation of the carrier polarity effect (electrons vs holes) on vacancy transport. Nevertheless, the validity of the model can be extended to different materials by a simple material-dependent parameter modification. Building upon the existing understanding of Schottky barrier height modulation, our study reveals three key insights─leveraging threshold voltage shifts to lower write bias; optimizing lattice temperature distribution and read bias polarity to achieve successful memory state recovery; engineering contact work function to overcome the detrimental parasitic current flow in short channel ambipolar memtransistors. Therefore, understanding the significant correlation between the switching mechanisms, different material systems, and device structures allows performance optimization of operating modes and device designs for future memtransistors-based computing systems.

Nanofloating gate modulated synaptic organic light-emitting transistors for reconfigurable displays

The use of postsynaptic current to drive long-lasting luminescence holds a disruptive potential for harnessing the next-generation of smart displays. Multiresponsive long afterglow emission can be achieved by integrating light-emitting polymers in electric spiked transistors trigged by distinct presynaptic signals inputs. Here, we report a highly effective electric spiked long afterglow organic light-emitting transistor (LAOLET), whose operation relies on a nanofloating gate architecture. Long afterglow emission with reconfigurable brightness and retention time is observed upon applying specific positive gate voltage spiked. Conversely, when negative gate voltage stimulus is applied, these LAOLETs function as click-on display. Interestingly, upon endowing the device with force sensing capabilities, it can operate as a long afterglow pressure sensor that emits long-lasting green light subsequently to a controlled extrusion action.

In-sensor image memorization and encoding via optical neurons for bio-stimulus domain reduction toward visual cognitive processing

As machine vision technology generates large amounts of data from sensors, it requires efficient computational systems for visual cognitive processing. Recently, in-sensor computing systems have emerged as a potential solution for reducing unnecessary data transfer and realizing fast and energy-efficient visual cognitive processing. However, they still lack the capability to process stored images directly within the sensor. Here, we demonstrate a heterogeneously integrated 1-photodiode and 1 memristor (1P-1R) crossbar for in-sensor visual cognitive processing, emulating a mammalian image encoding process to extract features from the input images. Unlike other neuromorphic vision processes, the trained weight values are applied as an input voltage to the image-saved crossbar array instead of storing the weight value in the memristors, realizing the in-sensor computing paradigm. We believe the heterogeneously integrated in-sensor computing platform provides an advanced architecture for real-time and data-intensive machine-vision applications via bio-stimulus domain reduction.

Designing in-sensor computing systems remains a challenge. Here, the authors demonstrate artificial optical neurons based on the in-sensor computing architecture that fuses sensory and computing nodes into a single platform capable of reducing data transfer time and energy for encoding and classification.

In-Memory Mathematical Operations with Spin-Orbit Torque Devices

Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI).  In-memory computing (IMC) offers a high performance and energy-efficient computing paradigm. To date, in-memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in-memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in-memory electrical current sensing units using spin-orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state-of-the-art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%.

Minimizing the Programming Power of Phase Change Memory by Using Graphene Nanoribbon Edge-Contact

Nonvolatile phase-change random access memory (PCRAM) is regarded as one of the promising candidates for emerging mass storage in the era of Big Data. However, relatively high programming energy hurdles the further reduction of power consumption in PCRAM. Utilizing narrow edge-contact of graphene can effectively reduce the active volume of phase change material in each cell, and therefore realize low-power operation. Here, it demonstrates that the power consumption can be reduced to ≈53.7 fJ in a cell with ≈3 nm-wide graphene nanoribbon (GNR) as edge-contact, whose cross-sectional area is only ≈1 nm² . It is found that the polarity of the bias pulse determines its cycle endurance in the asymmetric structure. If a positive bias is applied to the graphene electrode, the endurance can be extended at least one order longer than the case with a reversal of polarity. In addition, the introduction of the hexagonal boron nitride (h-BN) multilayer leads to a low resistance drift and a high programming speed in a memory cell. The work represents a great technological advance for the low-power PCRAM and can benefit in-memory computing in the future.

Generation of Multi-Lobe Chua Corsage Memristor and Its Neural Oscillation

The Chua corsage memristor (CCM) is considered as one of the candidates for the realization of biological neuron models due to its rich neuromorphic behaviors. In this paper, a universal model for m-lobe CCM memristor is proposed. Moreover, a novel small-signal equivalent circuit with one capacitor is derived based on the proposed model to determine the edge of chaos and obtain the zero-pole diagrams and analyze the frequency response and oscillation mechanism of the m-lobe CCM system, which are discussed in detail. In view of existence of the edge of chaos, the frequency response and the oscillation mechanism of the simplest oscillator is analysed using the proposed model. Finally, the proposed model has exhibited some essential neural oscillation, including the stable limit cycle, supercritical Hopf bifurcation, spiking and bursting oscillation. This study also reveals a previously undiscovered behavior of bursting oscillation in a CCM system.

Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance

Superlattice (SL) phase change materials have shown promise to reduce the switching current and resistance drift of phase change memory (PCM). However, the effects of internal SL interfaces and intermixing on PCM performance remain unexplored, although these are essential to understand and ensure reliable memory operation. Here, using nanometer-thin layers of Ge₂Sb₂Te₅ and Sb₂Te₃ in SL-PCM, we uncover that both switching current density (J_reset) and resistance drift coefficient (v) decrease as the SL period thickness is reduced (i.e., higher interface density); however, interface intermixing within the SL increases both. The signatures of distinct versus intermixed interfaces also show up in transmission electron microscopy, X-ray diffraction, and thermal conductivity measurements of our SL films. Combining the lessons learned, we simultaneously achieve low J_reset ≈ 3-4 MA/cm² and ultralow v ≈ 0.002 in mushroom-cell SL-PCM with ∼110 nm bottom contact diameter, thus advancing SL-PCM technology for high-density storage and neuromorphic applications.

Reservoir computing on a silicon platform with a ferroelectric field-effect transistor

Reservoir computing offers efficient processing of time-series data with exceptionally low training cost for real-time computing in edge devices where energy and hardware resources are limited. Here, we report reservoir computing hardware based on a ferroelectric field-effect transistor (FeFET) consisting of silicon and ferroelectric hafnium zirconium oxide. The rich dynamics originating from the ferroelectric polarization dynamics and polarization-charge coupling are the keys leading to the essential properties for reservoir computing: the short-term memory and high-dimensional nonlinear transform function. We demonstrate that an FeFET-based reservoir computing system can successfully solve computational tasks on time-series data processing including nonlinear time series prediction after training with simple regression. Due to the FeFET’s high feasibility of implementation on the silicon platform, the systems have flexibility in both device- and circuit-level designs, and have a high potential for on-chip integration with existing computing technologies towards the realization of advanced intelligent systems.

Kasidit Toprasertpong and colleagues describe reservoir computing hardware with potential for on-chip integration with existing computing technologies. The approach is based on a ferroelectric field-effect transistor, and can solve computational tasks on time series data including nonlinear time series prediction after training with simple regression.

Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications

Circuit or electronic components are useful elements allowing the realization of different circuit functionalities. The resistor, capacitor and inductor represent the three commonly known basic passive circuit elements owing to their fundamental nature relating them to the four circuit variables, namely voltage, magnetic flux, current and electric charge. The memory resistor (or memristor) was claimed to be the fourth basic passive circuit element, complementing the resistor, capacitor and inductor. This paper presents a review on the four basic passive circuit elements. After a brief recall on the first three known basic passive circuit elements, a thorough description of the memristor follows. Memristor sparks interest in the scientific community due to its interesting features, for example nano-scalability, memory capability, conductance modulation, connection flexibility and compatibility with CMOS technology, etc. These features among many others are currently in high demand on an industrial scale. For this reason, thousands of memristor-based applications are reported. Hence, the paper presents an in-depth overview of the philosophical argumentations of memristor, technologies and applications.

Heterogeneous Integration of Atomically Thin Semiconductors for Non-von Neumann CMOS

Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high-performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n-type TMDs such as MoS₂ and WS₂ grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p-type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n-type MoS₂ and p-type vanadium doped WSe₂ FETs with non-volatile and analog memory storage capabilities to achieve a non-von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n-type and p-type FETs, which is critical for any IC development. Inverters and a simplified 2-input-1-output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non-von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials.

Seizure Detection and Prediction by Parallel Memristive Convolutional Neural Networks

During the past two decades, epileptic seizure detection and prediction algorithms have evolved rapidly. However, despite significant performance improvements, their hardware implementation using conventional technologies, such as Complementary Metal-Oxide-Semiconductor (CMOS), in power and area-constrained settings remains a challenging task; especially when many recording channels are used. In this paper, we propose a novel low-latency parallel Convolutional Neural Network (CNN) architecture that has between 2-2,800x fewer network parameters compared to State-Of-The-Art (SOTA) CNN architectures and achieves 5-fold cross validation accuracy of 99.84% for epileptic seizure detection, and 99.01% and 97.54% for epileptic seizure prediction, when evaluated using the University of Bonn Electroencephalogram (EEG), CHB-MIT and SWEC-ETHZ seizure datasets, respectively. We subsequently implement our network onto analog crossbar arrays comprising Resistive Random-Access Memory (RRAM) devices, and provide a comprehensive benchmark by simulating, laying out, and determining hardware requirements of the CNN component of our system. We parallelize the execution of convolution layer kernels on separate analog crossbars to enable 2 orders of magnitude reduction in latency compared to SOTA hybrid Memristive-CMOS Deep Learning (DL) accelerators. Furthermore, we investigate the effects of non-idealities on our system and investigate Quantization Aware Training (QAT) to mitigate the performance degradation due to low Analog-to-Digital Converter (ADC)/Digital-to-Analog Converter (DAC) resolution. Finally, we propose a stuck weight offsetting methodology to mitigate performance degradation due to stuck [Formula: see text] memristor weights, recovering up to 32% accuracy, without requiring retraining. The CNN component of our platform is estimated to consume approximately 2.791 W of power while occupying an area of 31.255 mm² in a 22 nm FDSOI CMOS process.

Metaplastic and energy-efficient biocompatible graphene artificial synaptic transistors for enhanced accuracy neuromorphic computing

CMOS-based computing systems that employ the von Neumann architecture are relatively limited when it comes to parallel data storage and processing. In contrast, the human brain is a living computational signal processing unit that operates with extreme parallelism and energy efficiency. Although numerous neuromorphic electronic devices have emerged in the last decade, most of them are rigid or contain materials that are toxic to biological systems. In this work, we report on biocompatible bilayer graphene-based artificial synaptic transistors (BLAST) capable of mimicking synaptic behavior. The BLAST devices leverage a dry ion-selective membrane, enabling long-term potentiation, with ~50 aJ/µm2 switching energy efficiency, at least an order of magnitude lower than previous reports on two-dimensional material-based artificial synapses. The devices show unique metaplasticity, a useful feature for generalizable deep neural networks, and we demonstrate that metaplastic BLASTs outperform ideal linear synapses in classic image classification tasks. With switching energy well below the 1 fJ energy estimated per biological synapse, the proposed devices are powerful candidates for bio-interfaced online learning, bridging the gap between artificial and biological neural networks.

Cluster-type analogue memristor by engineering redox dynamics for high-performance neuromorphic computing

Memristors, or memristive devices, have attracted tremendous interest in neuromorphic hardware implementation. However, the high electric-field dependence in conventional filamentary memristors results in either digital-like conductance updates or gradual switching only in a limited dynamic range. Here, we address the switching parameter, the reduction probability of Ag cations in the switching medium, and ultimately demonstrate a cluster-type analogue memristor. Ti nanoclusters are embedded into densified amorphous Si for the following reasons: low standard reduction potential, thermodynamic miscibility with Si, and alloy formation with Ag. These Ti clusters effectively induce the electrochemical reduction activity of Ag cations and allow linear potentiation/depression in tandem with a large conductance range (~244) and long data retention (~99% at 1 hour). Moreover, according to the reduction potentials of incorporated metals (Pt, Ta, W, and Ti), the extent of linearity improvement is selectively tuneable. Image processing simulation proves that the Ti_4.8%:a-Si device can fully function with high accuracy as an ideal synaptic model.

Conventional filamentary memristors are limited in dynamics by the high electric-field dependence of the conductive filament. Here, Jeong et al. presents a method which creates a cluster-type memristor, enabling large conductance range and long data retention.

Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility. By introducing a medium-temperature oxidation in which the sputtered Ge atoms are oxidized at a relatively higher temperature compared with the ReRAM devices fabricated by physical vapor deposition at room temperature, higher device reliability has been acquired. Based on the empirically obtained device parameters, a PIM architecture has been conceived and a system-level evaluations have been performed in this work. Considerations include the cycle-to-cycle variation in the GeO_x ReRAM synapse, analog-to-digital converter resolution, synaptic array size, and interconnect latency for the system-level evaluation with the Canadian Institute for Advance Research-10 dataset. A fully Si processing-compatible and robust ReRAM synapse and its applicability for PIM are demonstrated.

Electronically Reconfigurable Photonic Switches Incorporating Plasmonic Structures and Phase Change Materials

The ever-increasing demands for data processing and storage will require seamless monolithic co-integration of electronics and photonics. Phase-change materials are uniquely suited to fulfill this function due to their dual electro-optical sensitivity, nonvolatile retention properties, and fast switching dynamics. The extreme size disparity however between CMOS electronics and dielectric photonics inhibits the realization of efficient and compact electrically driven photonic switches, logic and routing elements. Here, the authors achieve an important milestone in harmonizing the two domains by demonstrating an electrically reconfigurable, ultra-compact and nonvolatile memory that is optically accessible. The platform relies on localized heat, generated within a plasmonic structure; this uniquely allows for both optical and electrical readout signals to be interlocked with the material state of the PCM while still ensuring that the writing operation is electrically decoupled. Importantly, by miniaturization and effective thermal engineering, the authors achieve unprecedented energy efficiency, opening up a path towards low-energy optoelectronic hardware for neuromorphic and in-memory computing.

In-Memory Computing using Memristor Arrays with Ultrathin 2D PdSeOx /PdSe2 Heterostructure

In-memory computing based on memristor arrays holds promise to address the speed and energy issues of the classical von Neumann computing system. However, the stochasticity of ions' transport in conventional oxide-based memristors imposes severe intrinsic variability, which compromises learning accuracy and hinders the implementation of neural network hardware accelerators. Here, these challenges are addressed using a low-voltage memristor array based on an ultrathin PdSeO_x /PdSe₂ heterostructure switching medium realized by a controllable ultraviolet (UV)-ozone treatment. A distinctively different ions' transport mechanism is revealed in the heterostructure that can confine the formation of conductive filaments, leading to a remarkable uniform switching with low set and reset voltage variability values of 4.8% and -3.6%, respectively. Moreover, convolutional image processing is further implemented using various crossbar kernels that achieve a high recognition accuracy of ≈93.4% due to the highly linear and symmetric analog weight update as well as multiple conductance states, manifesting its potential beyond von Neumann computing.

Interface-Modulated Resistive Switching in Mo-Irradiated ReS2 for Neuromorphic Computing

Coupling charge impurity scattering effects and charge-carrier modulation by doping can offer intriguing opportunities for atomic-level control of resistive switching (RS). Nonetheless, such effects have remained unexplored for memristive applications based on 2D materials. Here a facile approach is reported to transform an RS-inactive rhenium disulfide (ReS₂ ) into an effective switching material through interfacial modulation induced by molybdenum-irradiation (Mo-i) doping. Using ReS₂ as a model system, this study unveils a unique RS mechanism based on the formation/dissolution of metallic β-ReO₂ filament across the defective ReS₂ interface during the set/reset process. Through simple interfacial modulation, ReS₂ of various thicknesses are switchable by modulating the Mo-irradiation period. Besides, the Mo-irradiated ReS₂ (Mo-ReS₂ ) memristor further exhibits a bipolar non-volatile switching ratio of nearly two orders of magnitude, programmable multilevel resistance states, and long-term synaptic plasticity. Additionally, the fabricated device can achieve a high MNIST learning accuracy of 91% under a non-identical pulse train. The study's findings demonstrate the potential for modulating RS in RS-inactive 2D materials via the unique doping-induced charged impurity scattering property.

Optimised weight programming for analogue memory-based deep neural networks

Analogue memory-based deep neural networks provide energy-efficiency and per-area throughput gains relative to state-of-the-art digital counterparts such as graphics processing units. Recent advances focus largely on hardware-aware algorithmic training and improvements to circuits, architectures, and memory devices. Optimal translation of software-trained weights into analogue hardware weights—given the plethora of complex memory non-idealities—represents an equally important task. We report a generalised computational framework that automates the crafting of complex weight programming strategies to minimise accuracy degradations during inference, particularly over time. The framework is agnostic to network structure and generalises well across recurrent, convolutional, and transformer neural networks. As a highly flexible numerical heuristic, the approach accommodates arbitrary device-level complexity, making it potentially relevant for a variety of analogue memories. By quantifying the limit of achievable inference accuracy, it also enables analogue memory-based deep neural network accelerators to reach their full inference potential.

Device-level complexity represents a big shortcoming for the hardware realization of analogue memory-based deep neural networks. Mackin et al. report a generalized computational framework, translating software-trained weights into analogue hardware weights, to minimise inference accuracy degradation.

Metal Halide Perovskite-Based Memristors for Emerging Memory Applications

There is an increased demand for next-generation memory devices with high density and fast operation speed to replace conventional memory devices. Memristors are promising candidates for next-generation memory devices because of their scalability, stable data retention, low power consumption, and fast operation. Among the various types of memristors, halide perovskites exhibit potential as emerging materials for memristors by using hysteresis based on the movement of defects or ions in halide perovskites. However, research on the implementation of perovskite materials as memristors is in its early stages; some challenges and problems must be solved to enable the practical application of halide perovskites for next-generation memory devices. From this perspective, we highlight the recent progress in memristors that use halide perovskites. Moreover, we introduce a strategy to enhance the performance and analyze the operation mechanism of memory devices that use halide perovskites. Finally, we summarize the challenges in the development of device technology to use halide perovskites in next-generation memory devices.