Memory devices and applications for in-memory computing

Stochastic Spiking Behavior in Neuromorphic Networks Enables True Random Number Generation

There is currently a great deal of interest in the use of nanoscale devices to emulate the behaviors of neurons and synapses and to facilitate brain-inspired computation. Here, it is shown that percolating networks of nanoparticles exhibit stochastic spiking behavior that is strikingly similar to that observed in biological neurons. The spiking rate can be controlled by the input stimulus, similar to "rate coding" in biology, and the distributions of times between events are log-normal, providing insights into the atomic-scale spiking mechanism. The stochasticity of the spiking behavior is then used for true random number generation, and the high quality of the generated random bit-streams is demonstrated, opening up promising routes toward integration of neuromorphic computing with secure information processing.

Atomic-Layer-Deposition-Based 2D Transition Metal Chalcogenides: Synthesis, Modulation, and Applications

Transition metal chalcogenides (TMCs) are a large family of 2D materials with different properties, and are promising candidates for a wide range of applications such as nanoelectronics, sensors, energy conversion, and energy storage. In the research of new materials, the development and investigation of industry-compatible synthesis techniques is of key importance. In this respect, it is important to study 2D TMC materials synthesized by the atomic layer deposition (ALD) technique, which is widely applied in industries. In addition to the synthesis of 2D TMCs, ALD is used to modulate the characteristic of 2D TMCs such as their carrier density and morphology. So far, the improvement of thin film uniformity without oxidation and the synthesis of low-dimensional nanomaterials on 2D TMCs have been the research focus. Herein, the synthesis and modulation of 2D TMCs by ALD is described, and the characteristics of ALD-based TMCs used in nanoelectronics, sensors, and energy applications are discussed.

Stimuli-Responsive Memristive Materials for Artificial Synapses and Neuromorphic Computing

Neuromorphic computing holds promise for building next-generation intelligent systems in a more energy-efficient way than the conventional von Neumann computing architecture. Memristive hardware, which mimics biological neurons and synapses, offers high-speed operation and low power consumption, enabling energy- and area-efficient, brain-inspired computing. Here, recent advances in memristive materials and strategies that emulate synaptic functions for neuromorphic computing are highlighted. The working principles and characteristics of biological neurons and synapses, which can be mimicked by memristive devices, are presented. Besides device structures and operation with different external stimuli such as electric, magnetic, and optical fields, how memristive materials with a rich variety of underlying physical mechanisms can allow fast, reliable, and low-power neuromorphic applications is also discussed. Finally, device requirements are examined and a perspective on challenges in developing memristive materials for device engineering and computing science is given.

Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors

Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS₂ transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR/XOR computations and the skewed SRAM cell can achieve in-memory NAND/NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

•

We demonstrate the symmetrical 4T2R and skewed 3T3R computing-in-memory SRAM

•

Both computing-in-memory SRAM cells consume six components, exhibiting higher area efficiency

•

The designed computing-in-memory SRAM cells support multiple Boolean logic operations

Statistical Analysis of Uniform Switching Characteristics of Ta2O5-Based Memristors by Embedding In-Situ Grown 2D-MoS2 Buffer Layers

A memristor based on emerging resistive random-access memory (RRAM) is a promising candidate for use as a next-generation neuromorphic computing device which overcomes the von Neumann bottleneck. Meanwhile, due to their unique properties, including atomically thin layers and surface smoothness, two-dimensional (2D) materials are being widely studied for implementation in the development of new information-processing electronic devices. However, inherent drawbacks concerning operational uniformities, such as device-to-device variability, device yield, and reliability, are huge challenges in the realization of concrete memristor hardware devices. In this study, we fabricated Ta₂O₅-based memristor devices, where a 2D-MoS₂ buffer layer was directly inserted between the Ta₂O₅ switching layer and the Ag metal electrode to improve uniform switching characteristics in terms of switching voltage, the distribution of resistance states, endurance, and retention. A 2D-MoS₂ layered buffer film with a 5 nm thickness was directly grown on the Ta₂O₅ switching layer by the atomic-pressure plasma-enhanced chemical vapor deposition (AP-PECVD) method, which is highly uniform and provided a superior yield of 2D-MoS₂ film. It was observed that the switching operation was dramatically stabilized via the introduction of the 2D-MoS₂ buffer layer compared to a pristine device without the buffer layer. It was assumed that the difference in mobility and reduction rates between Ta₂O₅ and MoS₂ caused the narrow localization of ion migration, inducing the formation of more stable conduction filament. In addition, an excellent yield of 98% was confirmed while showing cell-to-cell operation uniformity, and the extrinsic and intrinsic variabilities in operating the device were highly uniform. Thus, the introduction of a MoS₂ buffer layer could improve highly reliable memristor device switching operation.

Dopant-Tunable Ultrathin Transparent Conductive Oxides for Efficient Energy Conversion Devices

Ultrathin film-based transparent conductive oxides (TCOs) with a broad work function (WF) tunability are highly demanded for efficient energy conversion devices. However, reducing the film thickness below 50 nm is limited due to rapidly increasing resistance; furthermore, introducing dopants into TCOs such as indium tin oxide (ITO) to reduce the resistance decreases the transparency due to a trade-off between the two quantities. Herein, we demonstrate dopant-tunable ultrathin (≤ 50 nm) TCOs fabricated via electric field-driven metal implantation (m-TCOs; m = Ni, Ag, and Cu) without compromising their innate electrical and optical properties. The m-TCOs exhibit a broad WF variation (0.97 eV), high transmittance in the UV to visible range (89-93% at 365 nm), and low sheet resistance (30-60 Ω cm^-2). Experimental and theoretical analyses show that interstitial metal atoms mainly affect the change in the WF without substantial losses in optical transparency. The m-ITOs are employed as anode or cathode electrodes for organic light-emitting diodes (LEDs), inorganic UV LEDs, and organic photovoltaics for their universal use, leading to outstanding performances, even without hole injection layer for OLED through the WF-tailored Ni-ITO. These results verify the proposed m-TCOs enable effective carrier transport and light extraction beyond the limits of traditional TCOs.

Scalable massively parallel computing using continuous-time data representation in nanoscale crossbar array

The growth of connected intelligent devices in the Internet of Things has created a pressing need for real-time processing and understanding of large volumes of analogue data. The difficulty in boosting the computing speed renders digital computing unable to meet the demand for processing analogue information that is intrinsically continuous in magnitude and time. By utilizing a continuous data representation in a nanoscale crossbar array, parallel computing can be implemented for the direct processing of analogue information in real time. Here, we propose a scalable massively parallel computing scheme by exploiting a continuous-time data representation and frequency multiplexing in a nanoscale crossbar array. This computing scheme enables the parallel reading of stored data and the one-shot operation of matrix-matrix multiplications in the crossbar array. Furthermore, we achieve the one-shot recognition of 16 letter images based on two physically interconnected crossbar arrays and demonstrate that the processing and modulation of analogue information can be simultaneously performed in a memristive crossbar array.

Ultrafast machine vision with artificial neural network devices based on a GaN-based micro-LED array

GaN-based micro-LED is an emerging display and communication device, which can work as well as a photodetector, enabling possible applications in machine vision. In this work, we measured the characteristics of micro-LED based photodetector experimentally and proposed a feasible simulation of a novel artificial neural network (ANN) device for the first time based on a micro-LED based photodetector array, providing ultrafast imaging (∼133 million bins per second) and a high image recognition rate. The array itself constitutes a neural network, in which the synaptic weights are tunable by the bias voltage. It has the potentials to be integrated with novel machine vision and reconfigurable computing applications, acting as a role of acceleration and similar functionality expansion. Also, the multi-functionality of micro-LED broadens its application potentials of combining ANN with display and communication.

2D materials-based homogeneous transistor-memory architecture for neuromorphic hardware

[Figure: see text].

High-Throughput Calculations on the Decomposition Reactions of Off-Stoichiometry GeSbTe Alloys for Embedded Memories

Chalcogenide GeSbTe (GST) alloys are exploited as phase change materials in a variety of applications ranging from electronic non-volatile memories to neuromorphic and photonic devices. In most applications, the prototypical Ge2Sb2Te5 compound along the GeTe-Sb2Te3 pseudobinary line is used. Ge-rich GST alloys, off the pseudobinary tie-line with a crystallization temperature higher than that of Ge2Sb2Te5, are currently explored for embedded phase-change memories of interest for automotive applications. During crystallization, Ge-rich GST alloys undergo a phase separation into pure Ge and less Ge-rich alloys. The detailed mechanisms underlying this transformation are, however, largely unknown. In this work, we performed high-throughput calculations based on Density Functional Theory (DFT) to uncover the most favorable decomposition pathways of Ge-rich GST alloys. The knowledge of the DFT formation energy of all GST alloys in the central part of the Ge-Sb-Te ternary phase diagram allowed us to identify the cubic crystalline phases that are more likely to form during the crystallization of a generic GST alloy. This scheme is exemplified by drawing a decomposition map for alloys on the Ge-Ge1Sb2Te4 tie-line. A map of decomposition propensity is also constructed, which suggests a possible strategy to minimize phase separation by still keeping a high crystallization temperature.

Decision trees within a molecular memristor

Profuse dendritic-synaptic interconnections among neurons in the neocortex embed intricate logic structures enabling sophisticated decision-making that vastly outperforms any artificial electronic analogues^1-3. The physical complexity is far beyond existing circuit fabrication technologies: moreover, the network in a brain is dynamically reconfigurable, which provides flexibility and adaptability to changing environments^4-6. In contrast, state-of-the-art semiconductor logic circuits are based on threshold switches that are hard-wired to perform predefined logic functions. To advance the performance of logic circuits, we are re-imagining fundamental electronic circuit elements by expressing complex logic in nanometre-scale material properties. Here we use voltage-driven conditional logic interconnectivity among five distinct molecular redox states of a metal-organic complex to embed a 'thicket' of decision trees (composed of multiple if-then-else conditional statements) having 71 nodes within a single memristor. The resultant current-voltage characteristic of this molecular memristor (a 'memory resistor', a globally passive resistive-switch circuit element that axiomatically complements the set of capacitor, inductor and resistor) exhibits eight recurrent and history-dependent non-volatile switching transitions between two conductance levels in a single sweep cycle. The identity of each molecular redox state was determined with in situ Raman spectroscopy and confirmed by quantum chemical calculations, revealing the electron transport mechanism. Using simple circuits of only these elements, we experimentally demonstrate dynamically reconfigurable, commutative and non-commutative stateful logic in multivariable decision trees that execute in a single time step and can, for example, be applied as local intelligence in edge computing^7-9.

Artificial Graphene on Si Substrates: Fabrication and Transport Characteristics

Artificial graphene (AG) based on a honeycomb lattice of semiconductor quantum dots (QDs) has been of great interest for exploration and applications of massless Dirac Fermions in semiconductors thanks to the tunable interplay between the carrier interactions and the honeycomb topology. Here, an innovative strategy to realize AG on Si substrates is developed by fabricating a honeycomb lattice of Au nanodisks on a Si/GeSi quantum well. The lateral potential modulation induced by the nanoscale Au/Si Schottky junction results in the formation of quantum dots arranged in a honeycomb lattice to form AG. Nonlinear current-voltage curves of the AG reveal conductance phase transitions with switch on/off voltages, a large electric hysteresis loop, and a strong sharp current peak accompanied by a group of differential-conductance peaks and negative differential conductance around the switch-on voltage, which can be modulated by temperature and light. These features are interpreted by a model based on the Coulomb blockade effect, the collective resonant tunneling, and the coupling of holes in the AG. Our results not only demonstrate an approach to the formation but also will greatly stimulate the characterizations and the applications of innovative semiconductor-based AG.

Accelerating Inference of Convolutional Neural Networks Using In-memory Computing

In-memory computing (IMC) is a non-von Neumann paradigm that has recently established itself as a promising approach for energy-efficient, high throughput hardware for deep learning applications. One prominent application of IMC is that of performing matrix-vector multiplication in O(1) time complexity by mapping the synaptic weights of a neural-network layer to the devices of an IMC core. However, because of the significantly different pattern of execution compared to previous computational paradigms, IMC requires a rethinking of the architectural design choices made when designing deep-learning hardware. In this work, we focus on application-specific, IMC hardware for inference of Convolution Neural Networks (CNNs), and provide methodologies for implementing the various architectural components of the IMC core. Specifically, we present methods for mapping synaptic weights and activations on the memory structures and give evidence of the various trade-offs therein, such as the one between on-chip memory requirements and execution latency. Lastly, we show how to employ these methods to implement a pipelined dataflow that offers throughput and latency beyond state-of-the-art for image classification tasks.

Near-channel classifier: symbiotic communication and classification in high-dimensional space

Brain-inspired high-dimensional (HD) computing represents and manipulates data using very long, random vectors with dimensionality in the thousands. This representation provides great robustness for various classification tasks where classifiers operate at low signal-to-noise ratio (SNR) conditions. Similarly, hyperdimensional modulation (HDM) leverages the robustness of complex-valued HD representations to reliably transmit information over a wireless channel, achieving a similar SNR gain compared to state-of-the-art codes. Here, we first propose methods to improve HDM in two ways: (1) reducing the complexity of encoding and decoding operations by generating, manipulating, and transmitting bipolar or integer vectors instead of complex vectors; (2) increasing the SNR gain by 0.2 dB using a new soft-feedback decoder; it can also increase the additive superposition capacity of HD vectors up to 1.7\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}× in noise-free cases. Secondly, we propose to combine encoding/decoding aspects of communication with classification into a single framework by relying on multifaceted HD representations. This leads to a near-channel classification (NCC) approach that avoids transformations between different representations and the overhead of multiple layers of encoding/decoding, hence reducing latency and complexity of a wireless smart distributed system while providing robustness against noise and interference from other nodes. We provide a use-case for wearable hand gesture recognition with 5 classes from 64 EMG sensors, where the encoded vectors are transmitted to a remote node for either performing NCC, or reconstruction of the encoded data. In NCC mode, the original classification accuracy of 94% is maintained, even in the channel at SNR of 0 dB, by transmitting 10,000-bit vectors. We remove the redundancy by reducing the vector dimensionality to 2048-bit that still exhibits a graceful degradation: less than 6% accuracy loss is occurred in the channel at − 5 dB, and with the interference from 6 nodes that simultaneously transmit their encoded vectors. In the reconstruction mode, it improves the mean-squared error by up to 20 dB, compared to standard decoding, when transmitting 2048-dimensional vectors.

Low-Power Memristive Logic Device Enabled by Controllable Oxidation of 2D HfSe2 for In-Memory Computing

Memristive logic device is a promising unit for beyond von Neumann computing systems and 2D materials are widely used because of their controllable interfacial properties. Most of these 2D memristive devices, however, are made from semiconducting chalcogenides which fail to gate the off-state current. To this end, a crossbar device using 2D HfSe2 is fabricated, and then the top layers are oxidized into "high-k" dielectric HfSex Oy via oxygen plasma treatment, so that the cell resistance can be remarkably increased. This two-terminal Ti/HfSex Oy /HfSe2 /Au device exhibits excellent forming-free resistive switching performance with high switching speed (<50 ns), low operation voltage (<3 V), large switching window (103 ), and good data retention. Most importantly, the operation current and the power consumption reach 100 pA and 0.1 fJ to 0.1 pJ, much lower than other HfO based memristors. A functionally complete low-power Boolean logic is experimentally demonstrated using the memristive device, allowing it in the application of energy-efficient in-memory computing.

A Primer on Hyperdimensional Computing for iEEG Seizure Detection

A central challenge in today's care of epilepsy patients is that the disease dynamics are severely under-sampled in the currently typical setting with appointment-based clinical and electroencephalographic examinations. Implantable devices to monitor electrical brain signals and to detect epileptic seizures may significantly improve this situation and may inform personalized treatment on an unprecedented scale. These implantable devices should be optimized for energy efficiency and compact design. Energy efficiency will ease their maintenance by reducing the time of recharging, or by increasing the lifetime of their batteries. Biological nervous systems use an extremely small amount of energy for information processing. In recent years, a number of methods, often collectively referred to as brain-inspired computing, have also been developed to improve computation in non-biological hardware. Here, we give an overview of one of these methods, which has in particular been inspired by the very size of brains' circuits and termed hyperdimensional computing. Using a tutorial style, we set out to explain the key concepts of hyperdimensional computing including very high-dimensional binary vectors, the operations used to combine and manipulate these vectors, and the crucial characteristics of the mathematical space they inhabit. We then demonstrate step-by-step how hyperdimensional computing can be used to detect epileptic seizures from intracranial electroencephalogram (EEG) recordings with high energy efficiency, high specificity, and high sensitivity. We conclude by describing potential future clinical applications of hyperdimensional computing for the analysis of EEG and non-EEG digital biomarkers.

Emerging 2D Memory Devices for In-Memory Computing

It is predicted that the conventional von Neumann computing architecture cannot meet the demands of future data-intensive computing applications due to the bottleneck between the processing and memory units. To try to solve this problem, in-memory computing technology, where calculations are carried out in situ within each nonvolatile memory unit, has been intensively studied. Among various candidate materials, 2D layered materials have recently demonstrated many new features that have been uniquely exploited to build next-generation electronics. Here, the recent progress of 2D memory devices is reviewed for in-memory computing. For each memory configuration, their operation mechanisms and memory characteristics are described, and their pros and cons are weighed. Subsequently, their versatile applications for in-memory computing technology, including logic operations, electronic synapses, and random number generation are presented. Finally, the current challenges and potential strategies for future 2D in-memory computing systems are also discussed at the material, device, circuit, and architecture levels. It is hoped that this manuscript could give a comprehensive review of 2D memory devices and their applications in in-memory computing, and be helpful for this exciting research area.

The rise of intelligent matter

Artificial intelligence (AI) is accelerating the development of unconventional computing paradigms inspired by the abilities and energy efficiency of the brain. The human brain excels especially in computationally intensive cognitive tasks, such as pattern recognition and classification. A long-term goal is de-centralized neuromorphic computing, relying on a network of distributed cores to mimic the massive parallelism of the brain, thus rigorously following a nature-inspired approach for information processing. Through the gradual transformation of interconnected computing blocks into continuous computing tissue, the development of advanced forms of matter exhibiting basic features of intelligence can be envisioned, able to learn and process information in a delocalized manner. Such intelligent matter would interact with the environment by receiving and responding to external stimuli, while internally adapting its structure to enable the distribution and storage (as memory) of information. We review progress towards implementations of intelligent matter using molecular systems, soft materials or solid-state materials, with respect to applications in soft robotics, the development of adaptive artificial skins and distributed neuromorphic computing.

An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations

In-memory computing may enable multiply-accumulate (MAC) operations, which are the primary calculations used in artificial intelligence (AI). Performing MAC operations with high capacity in a small area with high energy efficiency remains a challenge. In this work, we propose a circuit architecture that integrates monolayer MoS₂ transistors in a two-transistor–one-capacitor (2T-1C) configuration. In this structure, the memory portion is similar to a 1T-1C Dynamic Random Access Memory (DRAM) so that theoretically the cycling endurance and erase/write speed inherit the merits of DRAM. Besides, the ultralow leakage current of the MoS₂ transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The electrical characteristics of a single MoS₂ transistor also allow analog computation by multiplying the drain voltage by the stored voltage on the capacitor. The sum-of-product is then obtained by converging the currents from multiple 2T-1C units. Based on our experiment results, a neural network is ex-situ trained for image recognition with 90.3% accuracy. In the future, such 2T-1C units can potentially be integrated into three-dimensional (3D) circuits with dense logic and memory layers for low power in-situ training of neural networks in hardware.

In standard computing architectures, memory and logic circuits are separated, a feature that slows matrix operations vital to deep learning algorithms. Here, the authors present an alternate in-memory architecture and demonstrate a feasible approach for analog matrix multiplication.

Engineered nanoparticle network models for autonomous computing

Materials that exhibit synaptic properties are a key target for our effort to develop computing devices that mimic the brain intrinsically. If successful, they could lead to high performance, low energy consumption, and huge data storage. A 2D square array of engineered nanoparticles (ENPs) interconnected by an emergent polymer network is a possible candidate. Its behavior has been observed and characterized using coarse-grained molecular dynamics (CGMD) simulations and analytical lattice network models. Both models are consistent in predicting network links at varying temperatures, free volumes, and E-field (E⃗) strengths. Hysteretic behavior, synaptic short-term plasticity and long-term plasticity-necessary for brain-like data storage and computing-have been observed in CGMD simulations of the ENP networks in response to E-fields. Non-volatility properties of the ENP networks were also confirmed to be robust to perturbations in the dielectric constant, temperature, and affine geometry.

Ray-based framework for state identification in quantum dot devices

Quantum dots (QDs) defined with electrostatic gates are a leading platform for a scalable quantum computing implementation. However, with increasing numbers of qubits, the complexity of the control parameter space also grows. Traditional measurement techniques, relying on complete or near-complete exploration via two-parameter scans (images) of the device response, quickly become impractical with increasing numbers of gates. Here we propose to circumvent this challenge by introducing a measurement technique relying on one-dimensional projections of the device response in the multidimensional parameter space. Dubbed the "ray-based classification (RBC) framework," we use this machine learning approach to implement a classifier for QD states, enabling automated recognition of qubit-relevant parameter regimes. We show that RBC surpasses the 82% accuracy benchmark from the experimental implementation of image-based classification techniques from prior work, while reducing the number of measurement points needed by up to 70%. The reduction in measurement cost is a significant gain for time-intensive QD measurements and is a step forward toward the scalability of these devices. We also discuss how the RBC-based optimizer, which tunes the device to a multiqubit regime, performs when tuning in the two-dimensional and three-dimensional parameter spaces defined by plunger and barrier gates that control the QDs. This work provides experimental validation of both efficient state identification and optimization with machine learning techniques for non-traditional measurements in quantum systems with high-dimensional parameter spaces and time-intensive measurements.

Reversible Barrier Switching of ZnO/RuO2 Schottky Diodes

The current-voltage characteristics of ZnO/RuO2 Schottky diodes prepared by magnetron sputtering are shown to exhibit a reversible hysteresis behavior, which corresponds to a variation of the Schottky barrier height between 0.9 and 1.3 eV upon voltage cycling. The changes in the barrier height are attributed to trapping and de-trapping of electrons in oxygen vacancies.

Synaptic transistors and neuromorphic systems based on carbon nano-materials

Carbon-based materials possessing a nanometer size and unique electrical properties perfectly address the two critical issues of transistors, the low power consumption and scalability, and are considered as a promising material in next-generation synaptic devices. In this review, carbon-based synaptic transistors were systematically summarized. In the carbon nanotube section, the synthesis of carbon nanotubes, purification of carbon nanotubes, the effect of architecture on the device performance and related carbon nanotube-based devices for neuromorphic computing were discussed. In the graphene section, the synthesis of graphene and its derivative, as well as graphene-based devices for neuromorphic computing, was systematically studied. Finally, the current challenges for carbon-based synaptic transistors were discussed.

Robust high-dimensional memory-augmented neural networks

Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapting to new data. Memory-augmented neural networks enhance neural networks with an explicit memory to overcome these issues. Access to this explicit memory, however, occurs via soft read and write operations involving every individual memory entry, resulting in a bottleneck when implemented using the conventional von Neumann computer architecture. To overcome this bottleneck, we propose a robust architecture that employs a computational memory unit as the explicit memory performing analog in-memory computation on high-dimensional (HD) vectors, while closely matching 32-bit software-equivalent accuracy. This is achieved by a content-based attention mechanism that represents unrelated items in the computational memory with uncorrelated HD vectors, whose real-valued components can be readily approximated by binary, or bipolar components. Experimental results demonstrate the efficacy of our approach on few-shot image classification tasks on the Omniglot dataset using more than 256,000 phase-change memory devices. Our approach effectively merges the richness of deep neural network representations with HD computing that paves the way for robust vector-symbolic manipulations applicable in reasoning, fusion, and compression.

The implementation of memory-augmented neural networks using conventional computer architectures is challenging due to a large number of read and write operations. Here, Karunaratne, Schmuck et al. propose an architecture that enables analog in-memory computing on high-dimensional vectors at accuracy matching 32-bit software equivalent.

In situ Parallel Training of Analog Neural Network Using Electrochemical Random-Access Memory

In-memory computing based on non-volatile resistive memory can significantly improve the energy efficiency of artificial neural networks. However, accurate in situ training has been challenging due to the nonlinear and stochastic switching of the resistive memory elements. One promising analog memory is the electrochemical random-access memory (ECRAM), also known as the redox transistor. Its low write currents and linear switching properties across hundreds of analog states enable accurate and massively parallel updates of a full crossbar array, which yield rapid and energy-efficient training. While simulations predict that ECRAM based neural networks achieve high training accuracy at significantly higher energy efficiency than digital implementations, these predictions have not been experimentally achieved. In this work, we train a 3 × 3 array of ECRAM devices that learns to discriminate several elementary logic gates (AND, OR, NAND). We record the evolution of the network's synaptic weights during parallel in situ (on-line) training, with outer product updates. Due to linear and reproducible device switching characteristics, our crossbar simulations not only accurately simulate the epochs to convergence, but also quantitatively capture the evolution of weights in individual devices. The implementation of the first in situ parallel training together with strong agreement with simulation results provides a significant advance toward developing ECRAM into larger crossbar arrays for artificial neural network accelerators, which could enable orders of magnitude improvements in energy efficiency of deep neural networks.

Recent Advances on Multivalued Logic Gates: A Materials Perspective

The recent advancements in multivalued logic gates represent a rapid paradigm shift in semiconductor technology toward a new era of hyper Moore's law. Particularly, the significant evolution of materials is guiding multivalued logic systems toward a breakthrough gradually, whereby they are transcending the limits of conventional binary logic systems in terms of all the essential figures of merit, i.e., power dissipation, operating speed, circuit complexity, and, of course, the level of the integration. In this review, recent advances in the field of multivalued logic gates based on emerging materials to provide a comprehensive guideline for possible future research directions are reviewed. First, an overview of the design criteria and figures of merit for multivalued logic gates is presented, and then advancements in various emerging nanostructured materials-ranging from 0D quantum dots to multidimensional heterostructures-are summarized and these materials in terms of device design criteria are assessed. The current technological challenges and prospects of multivalued logic devices are also addressed and major research trends are elucidated.

Materials Screening for Disorder-Controlled Chalcogenide Crystals for Phase-Change Memory Applications

Tailoring the degree of disorder in chalcogenide phase-change materials (PCMs) plays an essential role in nonvolatile memory devices and neuro-inspired computing. Upon rapid crystallization from the amorphous phase, the flagship Ge-Sb-Te PCMs form metastable rocksalt-like structures with an unconventionally high concentration of vacancies, which results in disordered crystals exhibiting Anderson-insulating transport behavior. Here, ab initio simulations and transport experiments are combined to extend these concepts to the parent compound of Ge-Sb-Te alloys, viz., binary Sb₂ Te₃ , in the metastable rocksalt-type modification. Then a systematic computational screening over a wide range of homologous, binary and ternary chalcogenides, elucidating the critical factors that affect the stability of the rocksalt structure is carried out. The findings vastly expand the family of disorder-controlled main-group chalcogenides toward many more compositions with a tunable bandgap size for demanding phase-change applications, as well as a varying strength of spin-orbit interaction for the exploration of potential topological Anderson insulators.

Emerging Opportunities for 2D Semiconductor/Ferroelectric Transistor-Structure Devices

Semiconductor technology, which is rapidly evolving, is poised to enter a new era for which revolutionary innovations are needed to address fundamental limitations on material and working principle level. 2D semiconductors inherently holding novel properties at the atomic limit show great promise to tackle challenges imposed by traditional bulk semiconductor materials. Synergistic combination of 2D semiconductors with functional ferroelectrics further offers new working principles, and is expected to deliver massively enhanced device performance for existing complementary metal-oxide-semiconductor (CMOS) technologies and add unprecedented applications for next-generation electronics. Herein, recent demonstrations of novel device concepts based on 2D semiconductor/ferroelectric heterostructures are critically reviewed covering their working mechanisms, device construction, applications, and challenges. In particular, emerging opportunities of CMOS-process-compatible 2D semiconductor/ferroelectric transistor structure devices for the development of a rich variety of applications are discussed, including beyond-Boltzmann transistors, nonvolatile memories, neuromorphic devices, and reconfigurable nanodevices such as p-n homojunctions and self-powered photodetectors. It is concluded that 2D semiconductor/ferroelectric heterostructures, as an emergent heterogeneous platform, could drive many more exciting innovations for modern electronics, beyond the capability of ubiquitous silicon systems.

Coupled VO2 Oscillators Circuit as Analog First Layer Filter in Convolutional Neural Networks

In this work we present an in-memory computing platform based on coupled VO₂ oscillators fabricated in a crossbar configuration on silicon. Compared to existing platforms, the crossbar configuration promises significant improvements in terms of area density and oscillation frequency. Further, the crossbar devices exhibit low variability and extended reliability, hence, enabling experiments on 4-coupled oscillator. We demonstrate the neuromorphic computing capabilities using the phase relation of the oscillators. As an application, we propose to replace digital filtering operation in a convolutional neural network with oscillating circuits. The concept is tested with a VGG13 architecture on the MNIST dataset, achieving performances of 95% in the recognition task.

Flexible boron nitride-based memristor for in situ digital and analogue neuromorphic computing applications

The data processing efficiency of traditional computers is suffering from the intrinsic limitation of physically separated processing and memory units. Logic-in-memory and brain-inspired neuromorphic computing are promising in-memory computing paradigms for improving the computing efficiency and avoiding high power consumption caused by extra data movement. However, memristors that can conduct digital memcomputing and neuromorphic computing simultaneously are limited by the difference in the information form between digital data and analogue data. In order to solve this problem, this paper proposes a flexible low-dimensional memristor based on boron nitride (BN), which has ultralow-power non-volatile memory characteristic, reliable digital memcomputing capabilities, and integrated ultrafast neuromorphic computing capabilities in a single in situ computing system. The logic-in-memory basis, including FALSE, material implication (IMP), and NAND, are implemented successfully. The power consumption of the proposed memristor per synaptic event (198 fJ) can be as low as biology (fJ level) and the response time (1 μs) of the neuromorphic computing is four orders of magnitude shorter than that of the human brain (10 ms), paving the way for wearable ultrahigh efficient next-generation in-memory computing architectures.

Bifunctional Silver-Doped ZnO for Reliable and Stable Organic-Inorganic Hybrid Perovskite Memory

Halide perovskites (HPs) have possible uses as an active layer for emerging memory devices due to their low operation voltage and high on/off ratio. However, HP-based memory devices, which are operated by the formation of a conductive filament, still suffer from reliability issues such as limited endurance and stability. To solve the problems, it is essential to control filament formation in the active layer. Here, we present nanoscale HP-based memory devices that have a Ag-doped ZnO (AZO) layer on HP. The AZO layer is used as a Ag ion reservoir for filament formation in HP, and this reservoir enables control of filament formation. By adjusting the Ag concentration in the AZO layer, the controlled filament composed of Ag can be formed; as a result, the memory device has excellent endurance (3 × 10⁴ cycles) compared to the device that uses a Ag electrode instead of an AZO layer (4 × 10² cycles). Also, an AZO layer can passivate HP, so the device operates stably in ambient air for 15 days with a high on/off ratio (10⁶). These results demonstrate that the introduction of the AZO layer can improve the reliability of HP-based memory devices for high-density applications.

Parallel convolutional processing using an integrated photonic tensor core

With the proliferation of ultrahigh-speed mobile networks and internet-connected devices, along with the rise of artificial intelligence (AI)¹, the world is generating exponentially increasing amounts of data that need to be processed in a fast and efficient way. Highly parallelized, fast and scalable hardware is therefore becoming progressively more important². Here we demonstrate a computationally specific integrated photonic hardware accelerator (tensor core) that is capable of operating at speeds of trillions of multiply-accumulate operations per second (10¹² MAC operations per second or tera-MACs per second). The tensor core can be considered as the optical analogue of an application-specific integrated circuit (ASIC). It achieves parallelized photonic in-memory computing using phase-change-material memory arrays and photonic chip-based optical frequency combs (soliton microcombs³). The computation is reduced to measuring the optical transmission of reconfigurable and non-resonant passive components and can operate at a bandwidth exceeding 14 gigahertz, limited only by the speed of the modulators and photodetectors. Given recent advances in hybrid integration of soliton microcombs at microwave line rates^3-5, ultralow-loss silicon nitride waveguides^6,7, and high-speed on-chip detectors and modulators, our approach provides a path towards full complementary metal-oxide-semiconductor (CMOS) wafer-scale integration of the photonic tensor core. Although we focus on convolutional processing, more generally our results indicate the potential of integrated photonics for parallel, fast, and efficient computational hardware in data-heavy AI applications such as autonomous driving, live video processing, and next-generation cloud computing services.

Field-effect at electrical contacts to two-dimensional materials

The inferior electrical contact to two-dimensional (2D) materials is a critical challenge for their application in post-silicon very large-scale integrated circuits. Electrical contacts were generally related to their resistive effect, quantified as contact resistance. With a systematic investigation, this work demonstrates a capacitive metal-insulator-semiconductor (MIS) field-effect at the electrical contacts to 2D materials: The field-effect depletes or accumulates charge carriers, redistributes the voltage potential, and gives rise to abnormal current saturation and nonlinearity. On one hand, the current saturation hinders the devices' driving ability, which can be eliminated with carefully engineered contact configurations. On the other hand, by introducing the nonlinearity to monolithic analog artificial neural network circuits, the circuits' perception ability can be significantly enhanced, as evidenced using a coronavirus disease 2019 (COVID-19) critical illness prediction model. This work provides a comprehension of the field-effect at the electrical contacts to 2D materials, which is fundamental to the design, simulation, and fabrication of electronics based on 2D materials.

ELECTRONIC SUPPLEMENTARY MATERIAL

Supplementary material (results of the simulation and SEM) is available in the online version of this article at 10.1007/s12274-021-3670-y.

Proof-of-PUF Enabled Blockchain: Concurrent Data and Device Security for Internet-of-Energy

A detailed review on the technological aspects of Blockchain and Physical Unclonable Functions (PUFs) is presented in this article. It stipulates an emerging concept of Blockchain that integrates hardware security primitives via PUFs to solve bandwidth, integration, scalability, latency, and energy requirements for the Internet-of-Energy (IoE) systems. This hybrid approach, hereinafter termed as PUFChain, provides device and data provenance which records data origins, history of data generation and processing, and clone-proof device identification and authentication, thus possible to track the sources and reasons of any cyber attack. In addition to this, we review the key areas of design, development, and implementation, which will give us the insight on seamless integration with legacy IoE systems, reliability, cyber resilience, and future research challenges.

Recent advances in optical and optoelectronic data storage based on luminescent nanomaterials

The substantial amount of data generated every second in the big data age creates a pressing requirement for new and advanced data storage techniques. Luminescent nanomaterials (LNMs) not only possess the same optical properties as their bulk materials but also have unique electronic and mechanical characteristics due to the strong constraints of photons and electrons at the nanoscale, enabling the development of revolutionary methods for data storage with superhigh storage capacity, ultra-long working lifetime, and ultra-low power consumption. In this review, we investigate the latest achievements in LNMs for constructing next-generation data storage systems, with a focus on optical data storage and optoelectronic data storage. We summarize the LNMs used in data storage, namely upconversion nanomaterials, long persistence luminescent nanomaterials, and downconversion nanomaterials, and their applications in optical data storage and optoelectronic data storage. We conclude by discussing the superiority of the two types of data storage and survey the prospects for the field.

Neuromorphic Engineering: From Biological to Spike-Based Hardware Nervous Systems

The human brain is a sophisticated, high-performance biocomputer that processes multiple complex tasks in parallel with high efficiency and remarkably low power consumption. Scientists have long been pursuing an artificial intelligence (AI) that can rival the human brain. Spiking neural networks based on neuromorphic computing platforms simulate the architecture and information processing of the intelligent brain, providing new insights for building AIs. The rapid development of materials engineering, device physics, chip integration, and neuroscience has led to exciting progress in neuromorphic computing with the goal of overcoming the von Neumann bottleneck. Herein, fundamental knowledge related to the structures and working principles of neurons and synapses of the biological nervous system is reviewed. An overview is then provided on the development of neuromorphic hardware systems, from artificial synapses and neurons to spike-based neuromorphic computing platforms. It is hoped that this review will shed new light on the evolution of brain-like computing.

Integration and Co-design of Memristive Devices and Algorithms for Artificial Intelligence

Memristive devices share remarkable similarities to biological synapses, dendrites, and neurons at both the physical mechanism level and unit functionality level, making the memristive approach to neuromorphic computing a promising technology for future artificial intelligence. However, these similarities do not directly transfer to the success of efficient computation without device and algorithm co-designs and optimizations. Contemporary deep learning algorithms demand the memristive artificial synapses to ideally possess analog weighting and linear weight-update behavior, requiring substantial device-level and circuit-level optimization. Such co-design and optimization have been the main focus of memristive neuromorphic engineering, which often abandons the “non-ideal” behaviors of memristive devices, although many of them resemble what have been observed in biological components. Novel brain-inspired algorithms are being proposed to utilize such behaviors as unique features to further enhance the efficiency and intelligence of neuromorphic computing, which calls for collaborations among electrical engineers, computing scientists, and neuroscientists.

Lead-Free Dual-Phase Halide Perovskites for Preconditioned Conducting-Bridge Memory

Organometallic and all-inorganic halide perovskites (HPs) have recently emerged as promising candidate materials for resistive switching (RS) nonvolatile memory due to their current-voltage hysteresis caused by fast ion migration. Lead-free and all-inorganic HPs have been researched for non-toxic and environmentally friendly RS memory devices. However, only HP-based devices with electrochemically active top electrode (TE) exhibit ultra-low operating voltages and high on/off ratio RS properties. The active TE easily reacts to halide ions in HP films, and the devices have a low device durability. Herein, RS memory devices based on an air-stable lead-free all-inorganic dual-phase HP (AgBi₂ I₇ -Cs₃ Bi₂ I₉ ) are successfully fabricated with inert metal electrodes. The devices with Au TE show filamentary RS behavior by conducting-bridge involving Ag cations in HPs with ultra-low operating voltages (<0.15 V), high on/off ratio (>10⁷ ), multilevel data storage, and long retention times (>5 × 10⁴ s). The use of a closed-loop pulse switching method improves reversible RS properties up to 10³ cycles with high on/off ratio above 10⁶ . With an extremely small bending radius of 1 mm, the devices are operable with reasonable RS characteristics. This work provides a promising material strategy for lead-free all-inorganic HP-based nonvolatile memory devices for practical applications.

Monitoring PSA levels as chemical state-variables in metal-oxide memristors

Medical interventions increasingly rely on biosensors that can provide reliable quantitative information. A longstanding bottleneck in realizing this, is various non-idealities that generate offsets and variable responses across sensors. Current mitigation strategies involve the calibration of sensors, performed in software or via auxiliary compensation circuitry thus constraining real-time operation and integration efforts. Here, we show that bio-functionalized metal-oxide memristors can be utilized for directly transducing biomarker concentration levels to discrete memory states. The introduced chemical state-variable is found to be dependent on the devices’ initial resistance, with its response to chemical stimuli being more pronounced for higher resistive states. We leverage this attribute along with memristors’ inherent state programmability for calibrating a biosensing array to render a homogeneous response across all cells. Finally, we demonstrate the application of this technology in detecting Prostate Specific Antigen in clinically relevant levels (ng/ml), paving the way towards applications in large multi-panel assays.

Ultrahigh drive current and large selectivity in GeS selector

Selector devices are indispensable components of large-scale nonvolatile memory and neuromorphic array systems. Besides the conventional silicon transistor, two-terminal ovonic threshold switching device with much higher scalability is currently the most industrially favored selector technology. However, current ovonic threshold switching devices rely heavily on intricate control of material stoichiometry and generally suffer from toxic and complex dopants. Here, we report on a selector with a large drive current density of 34 MA cm-2 and a ~106 high nonlinearity, realized in an environment-friendly and earth-abundant sulfide binary semiconductor, GeS. Both experiments and first-principles calculations reveal Ge pyramid-dominated network and high density of near-valence band trap states in amorphous GeS. The high-drive current capacity is associated with the strong Ge-S covalency and the high nonlinearity could arise from the synergy of the mid-gap traps assisted electronic transition and local Ge-Ge chain growth as well as locally enhanced bond alignment under high electric field.

In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory

Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.

Ferroelectric field-effect transistors for logic and in-situ memory applications

The separation of processing and memory units in von Neumann architecture creates issues with energy consumption and speed mismatches, which is a huge obstacle on the road of integrated-circuit development. Potentially, the excellent performance of two-dimensional materials field-effect transistors controlled by organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) polymer could clear the path for the development of next-generation microelectronics. Here, we combined P(VDF-TrFE) polymer and molybdenum disulfide (MoS2) nanoflakes to fabricate a horizontal dual-gate ferroelectric field-effect transistor (HDG-FeFET) device. This device can provide in-situ memory of logic results while processing the AND logic function. During the logic operations, the logic output state-1/state-0 current ratio approached 105. After 900 s, the corresponding non-volatile memory state-1/state-0 current ratio remains at 104. This type of transistor is expected to provide a promising in-memory computing solution for next-generation computing architecture.

Accurate deep neural network inference using computational phase-change memory

In-memory computing using resistive memory devices is a promising non-von Neumann approach for making energy-efficient deep learning inference hardware. However, due to device variability and noise, the network needs to be trained in a specific way so that transferring the digitally trained weights to the analog resistive memory devices will not result in significant loss of accuracy. Here, we introduce a methodology to train ResNet-type convolutional neural networks that results in no appreciable accuracy loss when transferring weights to phase-change memory (PCM) devices. We also propose a compensation technique that exploits the batch normalization parameters to improve the accuracy retention over time. We achieve a classification accuracy of 93.7% on CIFAR-10 and a top-1 accuracy of 71.6% on ImageNet benchmarks after mapping the trained weights to PCM. Our hardware results on CIFAR-10 with ResNet-32 demonstrate an accuracy above 93.5% retained over a one-day period, where each of the 361,722 synaptic weights is programmed on just two PCM devices organized in a differential configuration.

Experimental Demonstration of Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses

Spiking neural networks (SNN) are computational models inspired by the brain’s ability to naturally encode and process information in the time domain. The added temporal dimension is believed to render them more computationally efficient than the conventional artificial neural networks, though their full computational capabilities are yet to be explored. Recently, in-memory computing architectures based on non-volatile memory crossbar arrays have shown great promise to implement parallel computations in artificial and spiking neural networks. In this work, we evaluate the feasibility to realize high-performance event-driven in-situ supervised learning systems using nanoscale and stochastic analog memory synapses. For the first time, the potential of analog memory synapses to generate precisely timed spikes in SNNs is experimentally demonstrated. The experiment targets applications which directly integrates spike encoded signals generated from bio-mimetic sensors with in-memory computing based learning systems to generate precisely timed control signal spikes for neuromorphic actuators. More than 170,000 phase-change memory (PCM) based synapses from our prototype chip were trained based on an event-driven learning rule, to generate spike patterns with more than 85% of the spikes within a 25 ms tolerance interval in a 1250 ms long spike pattern. We observe that the accuracy is mainly limited by the imprecision related to device programming and temporal drift of conductance values. We show that an array level scaling scheme can significantly improve the retention of the trained SNN states in the presence of conductance drift in the PCM. Combining the computational potential of supervised SNNs with the parallel compute power of in-memory computing, this work paves the way for next-generation of efficient brain-inspired systems.

Mixed-Precision Deep Learning Based on Computational Memory

Deep neural networks (DNNs) have revolutionized the field of artificial intelligence and have achieved unprecedented success in cognitive tasks such as image and speech recognition. Training of large DNNs, however, is computationally intensive and this has motivated the search for novel computing architectures targeting this application. A computational memory unit with nanoscale resistive memory devices organized in crossbar arrays could store the synaptic weights in their conductance states and perform the expensive weighted summations in place in a non-von Neumann manner. However, updating the conductance states in a reliable manner during the weight update process is a fundamental challenge that limits the training accuracy of such an implementation. Here, we propose a mixed-precision architecture that combines a computational memory unit performing the weighted summations and imprecise conductance updates with a digital processing unit that accumulates the weight updates in high precision. A combined hardware/software training experiment of a multilayer perceptron based on the proposed architecture using a phase-change memory (PCM) array achieves 97.73% test accuracy on the task of classifying handwritten digits (based on the MNIST dataset), within 0.6% of the software baseline. The architecture is further evaluated using accurate behavioral models of PCM on a wide class of networks, namely convolutional neural networks, long-short-term-memory networks, and generative-adversarial networks. Accuracies comparable to those of floating-point implementations are achieved without being constrained by the non-idealities associated with the PCM devices. A system-level study demonstrates 172 × improvement in energy efficiency of the architecture when used for training a multilayer perceptron compared with a dedicated fully digital 32-bit implementation.