Charge-Ferroelectric Transition in Ultrathin Na0.5 Bi4.5 Ti4 O15 Flakes Probed via a Dual-Gated Full van der Waals Transistor

Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor

Two-dimensional (2D) transition metal dichalcogenides (TMDs) allow for atomic-scale manipulation, challenging the conventional limitations of semiconductor materials. This capability may overcome the short-channel effect, sparking significant advancements in electronic devices that utilize 2D TMDs. Exploring the dimension and performance limits of transistors based on 2D TMDs has gained substantial importance. This review provides a comprehensive investigation into these limits of the single 2D-TMD transistor. It delves into the impacts of miniaturization, including the reduction of channel length, gate length, source/drain contact length, and dielectric thickness on transistor operation and performance. In addition, this review provides a detailed analysis of performance parameters such as source/drain contact resistance, subthreshold swing, hysteresis loop, carrier mobility, on/off ratio, and the development of p-type and single logic transistors. This review details the two logical expressions of the single 2D-TMD logic transistor, including current and voltage. It also emphasizes the role of 2D TMD-based transistors as memory devices, focusing on enhancing memory operation speed, endurance, data retention, and extinction ratio, as well as reducing energy consumption in memory devices functioning as artificial synapses. This review demonstrates the two calculating methods for dynamic energy consumption of 2D synaptic devices. This review not only summarizes the current state of the art in this field but also highlights potential future research directions and applications. It underscores the anticipated challenges, opportunities, and potential solutions in navigating the dimension and performance boundaries of 2D transistors.

Integration of Ultrathin Hafnium Oxide with a Clean van der Waals Interface for Two-Dimensional Sandwich Heterostructure Electronics

Integrating high-κ dielectrics with a small equivalent oxide thickness (EOT) with two-dimensional (2D) semiconductors for low-power consumption van der Waals (vdW) heterostructure electronics remains challenging in meeting both interface quality and dielectric property requirements. Here, we demonstrate the integration of ultrathin amorphous HfOx sandwiched within vdW heterostructures by the selective thermal oxidation of HfSe2 precursors. The self-cleaning process ensures a high-quality interface with a low interface state density of 1011-1012 cm-2 eV-1. The synthesized HfOx displays excellent dielectric properties with an EOT of ∼1.5 nm, i.e., a high κ of ∼16, an ultralow leakage current of 10-6 A/cm2, and an impressively high breakdown field of 9.5 MV/cm. This facilitates low-power consumption vdW heterostructure MoS2 transistors, demonstrating steep switching with a low subthreshold swing of 61 mV/decade. This one-step integration of high-κ dielectrics into vdW sandwich heterostructures holds immense potential for developing low-power consumption 2D electronics while meeting comprehensive dielectric requirements.

Quasi-Zero-Dimensional Ferroelectric Polarization Charges-Coupled Resistance Switching with High-Current Density in Ultrascaled Semiconductors

Ferroelectric memristors hold immense promise for advanced memory and neuromorphic computing. However, they face limitations due to low readout current density in conventional designs with low-conductive ferroelectric channels, especially at the nanoscale. Here, we report a ferroelectric-mediated memristor utilizing a 2D MoS2 nanoribbon channel with an ultrascaled cross-sectional area of <1000 nm2, defined by a ferroelectric BaTiO3 nanoribbon stacked on top. Strikingly, the Schottky barrier at the MoS2 contact can be effectively tuned by the charge transfers coupled with quasi-zero-dimensional polarization charges formed at the two ends of the nanoribbon, which results in distinctive resistance switching accompanied by multiple negative differential resistance showing the high-current density of >104 A/cm2. The associated space charges in BaTiO3 are minimized to ∼3.7% of the polarization charges, preserving nonvolatile polarization. This achievement establishes ferroelectric-mediated nanoscale semiconductor memristors with high readout current density as promising candidates for memory and highly energy-efficient in-memory computing applications.

Low-voltage ultrafast nonvolatile memory via direct charge injection through a threshold resistive-switching layer

The explosion in demand for massive data processing and storage requires revolutionary memory technologies featuring ultrahigh speed, ultralong retention, ultrahigh capacity and ultralow energy consumption. Although a breakthrough in ultrafast floating-gate memory has been achieved very recently, it still suffers a high operation voltage (tens of volts) due to the Fowler-Nordheim tunnelling mechanism. It is still a great challenge to realize ultrafast nonvolatile storage with low operation voltage. Here we propose a floating-gate memory with a structure of MoS2/hBN/MoS2/graphdiyne oxide/WSe2, in which a threshold switching layer, graphdiyne oxide, instead of a dielectric blocking layer in conventional floating-gate memories, is used to connect the floating gate and control gate. The volatile threshold switching characteristic of graphdiyne oxide allows the direct charge injection from control gate to floating gate by applying a nanosecond voltage pulse (20 ns) with low magnitude (2 V), and restricts the injected charges in floating gate for a long-term retention (10 years) after the pulse. The high operation speed and low voltage endow the device with an ultralow energy consumption of 10 fJ. These results demonstrate a new strategy to develop next-generation high-speed low-energy nonvolatile memory.

Remarkable ferroelectricity-modulated electronic and magnetic properties in a 2H-VS2/BiAlO3(0001) hybrid system

In the present work, a 2H-VS₂/BiAlO₃(0001) hybrid system is constructed to perform first-principles density functional theory (DFT) calculations. The results reveal that, in addition to the ionic-vdW interface coupling, the ferromagnetic semiconductive 2H-VS₂ monolayer on the ferroelectric BiAlO₃(0001) substrate exhibits n-type or p-type doping behavior and even half-metal characteristics. Furthermore, the magnetoelectric coefficient (α_S) for the 2H-VS₂/BiAlO₃(0001) structures can reach a value of 10^-10 G cm² V^-1 with ferroelectric polarization reversal. The estimated Curie temperatures (T_c) of the 2H-VS₂ monolayer on the BiAlO₃(0001) Z+ (positive), Z+↓ (polarization-reversed Z+), Z- (negative), and Z-↑ (polarization-reversed Z-) polar surfaces were found to be 176, 276, 266, and 87 K, respectively. This indicates that the magnetic properties of the 2H-VS₂ monolayer are remarkably tunable using a ferroelectric BiAlO₃(0001) knob. These important findings provide a distinctive treatment option for controllable and adjustable nanoelectronic, photoelectronic, and spintronic devices based on a 2H-VS₂ monolayer.

Asymmetric Ferroelectric-Gated Two-Dimensional Transistor Integrating Self-Rectifying Photoelectric Memory and Artificial Synapse

Ferroelectric field-effect transistors (Fe-FET) are promising candidates for future information devices. However, they suffer from low endurance and short retention time, which retards the application of processing memory in the same physical processes. Here, inspired by the ferroelectric proximity effects, we design a reconfigurable two-dimensional (2D) MoS₂ transistor featuring with asymmetric ferroelectric gate, exhibiting high memory and logic ability with a program/erase ratio of over 10⁶ and a self-rectifying ratio of 10³. Interestingly, the robust electric and optic cycling are obtained with a large switching ratio of 10⁶ and nine distinct resistance states upon optical excitation with excellent nonvolatile characteristics. Meanwhile, the operation of memory mimics the synapse behavior in response to light spikes with different intensity and number. This design realizes an integration of robust processing memory in one single device, which demonstrates a considerable potential of an asymmetric ferroelectric gate in the development of Fe-FETs for logic processing and nonvolatile memory applications.

Fermi Level Pinning Dependent 2D Semiconductor Devices: Challenges and Prospects

Motivated by the high expectation for efficient electrostatic modulation of charge transport at very low voltages, atomically thin 2D materials with a range of bandgaps are investigated extensively for use in future semiconductor devices. However, researchers face formidable challenges in 2D device processing mainly originated from the out-of-plane van der Waals (vdW) structure of ultrathin 2D materials. As major challenges, untunable Schottky barrier height and the corresponding strong Fermi level pinning (FLP) at metal interfaces are observed unexpectedly with 2D vdW materials, giving rise to unmodulated semiconductor polarity, high contact resistance, and lowered device mobility. Here, FLP observed from recently developed 2D semiconductor devices is addressed differently from those observed from conventional semiconductor devices. It is understood that the observed FLP is attributed to inefficient doping into 2D materials, vdW gap present at the metal interface, and hybridized compounds formed under contacting metals. To provide readers with practical guidelines for the design of 2D devices, the impact of FLP occurring in 2D semiconductor devices is further reviewed by exploring various origins responsible for the FLP, effects of FLP on 2D device performances, and methods for improving metallic contact to 2D materials.

Reconfigurable Quasi-Nonvolatile Memory/Subthermionic FET Functions in Ferroelectric-2D Semiconductor vdW Architectures

The functional reconfiguration of transistors and memory in homogenous ferroelectric devices offers significant opportunities for implementing the concepts of in-memory computing and logic-memory monolithic integration. Thus far, reconfiguration is realized through programmable doping profiles in the semiconductor channel using multiple-gate operation. This complex device architecture limits further scaling to match the overall chip requirements. Here, reconfigurable memory/transistor functionalities in a ferroelectric-gated van der Waals transistor by controlling the behavior of ferroelectric oxygen vacancies at the interface are demonstrated. Short- and long-term memory functions are demonstrated by modulating the border oxygen vacancy distribution and the associated charge dynamics. The quasi-nonvolatile long-term memory exhibits data retention of over 10⁵ s and endurance of up to 5 × 10⁵ cycles, verifying its applicability as a potential device platform for neuromorphic networks. More importantly, by modulating the ferroelectricity of the interfacial domains with the interactions of oxygen vacancies, a hysteresis-free logic transistor is realized with a subthermionic subthreshold swing down to 46 mV dec^-1 , which resembles a negative-capacitance field-effect transistor. The new concept of achieving functional reconfiguration with prior device performance in a single-gate ferroelectric field-effect transistor is of great advantage in future integrated circuit applications.

2D Heterostructures for Ubiquitous Electronics and Optoelectronics: Principles, Opportunities, and Challenges

A grand family of two-dimensional (2D) materials and their heterostructures have been discovered through the extensive experimental and theoretical efforts of chemists, material scientists, physicists, and technologists. These pioneering works contribute to realizing the fundamental platforms to explore and analyze new physical/chemical properties and technological phenomena at the micro-nano-pico scales. Engineering 2D van der Waals (vdW) materials and their heterostructures via chemical and physical methods with a suitable choice of stacking order, thickness, and interlayer interactions enable exotic carrier dynamics, showing potential in high-frequency electronics, broadband optoelectronics, low-power neuromorphic computing, and ubiquitous electronics. This comprehensive review addresses recent advances in terms of representative 2D materials, the general fabrication methods, and characterization techniques and the vital role of the physical parameters affecting the quality of 2D heterostructures. The main emphasis is on 2D heterostructures and 3D-bulk (3D) hybrid systems exhibiting intrinsic quantum mechanical responses in the optical, valley, and topological states. Finally, we discuss the universality of 2D heterostructures with representative applications and trends for future electronics and optoelectronics (FEO) under the challenges and opportunities from physical, nanotechnological, and material synthesis perspectives.

Electrostatic Modulation and Mechanism of the Electronic Properties of Monolayer MoS2 via Ferroelectric BiAlO3(0001) Polar Surfaces

In the present work, first-principles density functional theory calculations were carried out to explore the intrinsic interface coupling and electrostatic modulation as well as the effect of ferroelectric polarization reversal in the MoS₂/BiAlO₃(0001) [MoS₂/BAO(0001)] hybrid system. In addition to the interaction mechanism of the large ionic-van der Waals (vdW) coupling, our results indicate that the electronic properties of monolayer MoS₂ on the BAO(0001) polar surface can be effectively modulated by reversing the ferroelectric polarization and/or engineering the domain structures of the substrate. Due to the unusual charge transfer between the MoS₂ overlayer and the down-polarized ferroelectric BAO(0001) substrate, in the final analysis, the physical mechanism determining the interfacial charge transfer in the MoS₂/BAO(0001) hybrid system is attributed to the specific band alignment between the clean BAO(0001) surface and the freestanding monolayer MoS₂. Furthermore, our study predicts that MoS₂-based ferroelectric field-effect transistors and various types of seamless p-i, n-i, p-n, p⁺-p, and n⁺-n homojunctions possessing an extremely steep built-in electric field can be fabricated by reversing the ferroelectric polarization and/or patterning the domain structure of the BAO(0001) substrate.