Many-Body Molecular Interactions in a Memristor

Memristor-Based Artificial Chips

Memristors, promising nanoelectronic devices with in-memory resistive switching behavior that is assembled with a physically integrated core processing unit (CPU) and memory unit and even possesses highly possible multistate electrical behavior, could avoid the von Neumann bottleneck of traditional computing devices and show a highly efficient ability of parallel computation and high information storage. These advantages position them as potential candidates for future data-centric computing requirements and add remarkable vigor to the research of next-generation artificial intelligence (AI) systems, particularly those that involve brain-like intelligence applications. This work provides an overview of the evolution of memristor-based devices, from their initial use in creating artificial synapses and neural networks to their application in developing advanced AI systems and brain-like chips. It offers a broad perspective of the key device primitives enabling their special applications from the view of materials, nanostructure, and mechanism models. We highlight these demonstrations of memristor-based nanoelectronic devices that have potential for use in the field of brain-like AI, point out the existing challenges of memristor-based nanodevices toward brain-like chips, and propose the guiding principle and promising outlook for future device promotion and system optimization in the biomedical AI field.

Energy and Space Efficient Parallel Adder Using Molecular Memristors

A breakthrough in in-memory computing technologies hinges on the development of appropriate material platforms that can overcome their existing limitations, such as larger than optimal footprint and multiple serial computational steps, with potential accumulation of errors. Using a molecular switching element with multiple non-monotonic and deterministic transitions, the device count and the number of computational steps can be substantially reduced. With molecular materials, however, the realization of a reliable and robust platform is an unattained goal for decades. Here, crossbar arrays with up to 64 molecular memristors are fabricated to experimentally demonstrate 8-bit serial and 4-bit parallel adders that operate for thousands of measurement cycles with an estimated error probability of 10-16 . For performance benchmarking, a 32-bit parallel adder is designed and simulated with 268 million inputs including contributions from the peripheral circuitry showing a 47× higher energy efficiency, 93× faster operation, and 9% of the footprint, leading to 4390 times improved energy-delay product compared to a special purpose complementary metal-oxide-semiconductor (CMOS)-based multicore adder.