Self-aligned sub-10-nm nanogap electrode array for large-scale integration

Fabrication of sub-1 nm gap electrodes using metal-mask patterning and conductivity measurements of molecules in nanoscale spaces

Fabrications of sub-1 nm gap Au electrodes using a metal mask for patterning were achieved. Because the procedure does not involve wet processing, the ranges of possible electrode and substrate materials for the electrodes are greatly expanded.

Sub-15-nm patterning of asymmetric metal electrodes and devices by adhesion lithography

Coplanar electrodes formed from asymmetric metals separated on the nanometre length scale are essential elements of nanoscale photonic and electronic devices. Existing fabrication methods typically involve electron-beam lithography—a technique that enables high fidelity patterning but suffers from significant limitations in terms of low throughput, poor scalability to large areas and restrictive choice of substrate and electrode materials. Here, we describe a versatile method for the rapid fabrication of asymmetric nanogap electrodes that exploits the ability of selected self-assembled monolayers to attach conformally to a prepatterned metal layer and thereby weaken adhesion to a subsequently deposited metal film. The method may be carried out under ambient conditions using simple equipment and a minimum of processing steps, enabling the rapid fabrication of nanogap electrodes and optoelectronic devices with aspect ratios in excess of 100,000.

Electron-beam lithography is often used for patterning of asymmetric metal electrodes for nanoscale devices, but suffers from several limitations. Here, the authors report a new adhesion lithography process, which allows for high-throughput and simple fabrication of nanogap metal electrodes.

Self-aligned formation of sub 1 nm gaps utilizing electromigration during metal deposition

We developed a procedure for the fabrication of sub 1 nm gap Au electrodes via electromigration. Self-aligned nanogap formation was achieved by applying a bias voltage, which causes electromigration during metal evaporation. We also demonstrated the application of this method for the formation of nanogaps as small as 1 nm in width, and we found that the gap size can be controlled by changing the magnitude of the applied voltage. On the basis of the electric conductance and surface-enhanced Raman scattering (SERS) measurements, the fabricated gap size was estimated to be nearly equal to the molecular length of 1,4-benzenedithiol (BDT). Compared with existing electromigration methods, the new method provides two advantages: the process currents are clearly suppressed and parallel or large area production is possible. This simple method for the fabrication of a sub 1 nm gap electrode is useful for single-molecule-sized electronics and opens the door to future research on integrated sub 1 nm sized nanogap devices.

Fabrication of a carbon-nanotube-based field-effect transistor by microcontact printing

The fabrication of a field-effect transistor with both channel material and source and drain electrodes made from carbon nanotubes (CNTs) through patterned deposition of CNT films by microcontact printing is described. Surfactant-dispersed single-walled CNTs are first separated into semiconducting and metallic fractions by gel filtration. The semiconducting and metallic CNTs are then sequentially transferred by dendrimer-coated polydimethylsiloxane stamps onto dendrimer-coated silicon wafers following a printing protocol optimized for this purpose. The resulting CNT micropatterns are visualized by atomic force microscopy. Semiconducting as well as metallic CNTs preserve their characteristic electronic properties within the transferred films. A device composed of a rather thick (ca. 5 nm) and densely patterned film of metallic CNTs cross-printed on top of a thinner (ca. 1.5 nm) and less dense film of semiconducting CNTs shows the typical properties of a field-effect transistor with the metallic CNT stripes as electrodes, the semiconductive CNT stripes as channel material, and the silicon substrate as gate electrode.