2D Material-Enabled Optical Rectennas with Ultrastrong Light-Electron Coupling

Quantum Graphene Asymmetric Devices for Harvesting Electromagnetic Energy

We present here the fabrication at the wafer level and the electrical performance of two types of graphene diodes: ballistic trapezoidal-shaped graphene diodes and lateral tunneling graphene diodes. In the case of the ballistic trapezoidal-shaped graphene diode, we observe a large DC current of 200 µA at a DC bias voltage of ±2 V and a large voltage responsivity of 2000 v/w, while in the case of the lateral tunneling graphene diodes, we obtain a DC current of 1.5 mA at a DC bias voltage of ±2 V, with a voltage responsivity of 3000 v/w. An extended analysis of the defects produced during the fabrication process and their influences on the graphene diode performance is also presented.

Self-Expansion Based Multi-Patterning for 2D Materials Fabrication beyond the Lithographical Limit

Two-dimensional (2D) materials are promising successors for silicon transistor channels in ultimately scaled devices, necessitating significant research efforts to study their behavior at nanoscopic length scales. Unfortunately, current research has limited itself to direct patterning approaches, which limit the achievable resolution to the diffraction limit and introduce unwanted defects into the 2D material. The potential of multi-patterning to fabricate 2D materials features with unprecedented precision and low complexity at large scale is demonstrated here. By combining lithographic patterning of a mandrel and bottom-up self-expansion, this approach enables pattern resolution one order of magnitude below the lithographical resolution. In-depth characterization of the self-expansion double patterning (SEDP) process reveals the ability to manipulate the critical dimension with nanometer precision through a self-limiting and temperature-controlled oxidation process. These results indicate that the SEDP process can regain the quality and morphology of the 2D material, as shown by high-resolution microscopy and optical spectroscopy. This approach is shown to open up new avenues for research into high-performance, ultra-scaled 2D materials devices for future electronics.

Metasurface-Based Quantum Searcher on a Silicon-On-Insulator Chip

Optical analog computing has natural advantages of parallel computation, high speed and low energy consumption over traditional digital computing. To date, research in the field of on-chip optical analog computing has mainly focused on classical mathematical operations. Despite the advantages of quantum computing, on-chip quantum analog devices based on metasurfaces have not been demonstrated so far. In this work, based on a silicon-on-insulator (SOI) platform, we illustrated an on-chip quantum searcher with a characteristic size of 60 × 20 μm². We applied classical waves to simulate the quantum search algorithm based on the superposition principle and interference effect, while combining it with an on-chip metasurface to realize modulation capability. The marked items are found when the incident waves are focused on the marked positions, which is precisely the same as the efficiency of the quantum search algorithm. The proposed on-chip quantum searcher facilitates the miniaturization and integration of wave-based signal processing systems.