Dielectric Relaxation of La-Doped Zirconia Caused by Annealing Ambient

Structure and Dielectric Property of High-k ZrO2 Films Grown by Atomic Layer Deposition Using Tetrakis(Dimethylamido)Zirconium and Ozone

High-k metal oxide films are vital for the future development of microelectronics technology. In this work, ZrO₂ films were grown on silicon by atomic layer deposition (ALD) using tetrakis(dimethylamido)zirconium and ozone as precursors. The relatively constant deposition rate of 0.125 nm/cycle is obtained within the ALD temperature window of 200-250 °C. The film thickness can be precisely controlled by regulating the number of ALD cycle. The ZrO₂ films formed at 200-250 °C have an O/Zr atomic ratio of 1.85-1.9 and a low content of carbon impurity. ZrO₂ film begins to crystallize in ALD process above 210 °C, and the crystal structure is changed from cubic and orthorhombic phases to monoclinic and orthorhombic phases with increasing the deposition temperature to 350 °C. Moreover, the effect of annealing temperature on dielectric properties of ZrO₂ film was studied utilizing ZrO₂-based MIS device. The growth of the interface layer between ZrO₂ and Si substrate leads to the decrease in the capacitance and the leakage current of dielectric layer in the MIS device after 1000 °C annealing. ZrO₂ film exhibits the relatively high dielectric constant of 32.57 at 100 kHz and the low leakage current density of 3.3 × 10^-6 A cm^-2 at 1 MV/cm.

Hysteresis in Lanthanide Zirconium Oxides Observed Using a Pulse CV Technique and including the Effect of High Temperature Annealing

A powerful characterization technique, pulse capacitance-voltage (CV) technique, was used to investigate oxide traps before and after annealing for lanthanide zirconium oxide thin films deposited on n-type Si (111) substrates at 300 °C by liquid injection Atomic Layer Deposition (ALD). The results indicated that: (1) more traps were observed compared to the conventional capacitance-voltage characterization method in LaZrO_x; (2) the time-dependent trapping/de-trapping was influenced by the edge time, width and peak-to-peak voltage of a gate voltage pulse. Post deposition annealing was performed at 700 °C, 800 °C and 900 °C in N₂ ambient for 15 s to the samples with 200 ALD cycles. The effect of the high temperature annealing on oxide traps and leakage current were subsequently explored. It showed that more traps were generated after annealing with the trap density increasing from 1.41 × 10¹² cm⁻² for as-deposited sample to 4.55 × 10¹² cm⁻² for the 800 °C annealed one. In addition, the leakage current density increase from about 10⁻⁶ A/cm² at V_g = +0.5 V for the as-deposited sample to 10⁻³ A/cm² at V_g = +0.5 V for the 900 °C annealed one.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future.

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm

Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and increasing integration are that they enable lower manufacturing cost as well as higher performance. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. The paper reviews the advanced research status concerning charge trapping memory with high-k dielectrics for the performance improvement. Application of high-k dielectric as charge trapping layer, blocking layer, and tunneling layer is comprehensively discussed accordingly.

Dielectric relaxation of high-k oxides

Frequency dispersion of high-k dielectrics was observed and classified into two parts: extrinsic cause and intrinsic cause. Frequency dependence of dielectric constant (dielectric relaxation), that is the intrinsic frequency dispersion, could not be characterized before considering the effects of extrinsic frequency dispersion. Several mathematical models were discussed to describe the dielectric relaxation of high-k dielectrics. For the physical mechanism, dielectric relaxation was found to be related to the degree of polarization, which depended on the structure of the high-k material. It was attributed to the enhancement of the correlations among polar nanodomain. The effect of grain size for the high-k materials' structure mainly originated from higher surface stress in smaller grain due to its higher concentration of grain boundary.

Grain size dependence of dielectric relaxation in cerium oxide as high-k layer

Cerium oxide (CeO2) thin films used liquid injection atomic layer deposition (ALD) for deposition and ALD procedures were run at substrate temperatures of 150°C, 200°C, 250°C, 300°C, and 350°C, respectively. CeO2 were grown on n-Si(100) wafers. Variations in the grain sizes of the samples are governed by the deposition temperature and have been estimated using Scherrer analysis of the X-ray diffraction patterns. The changing grain size correlates with the changes seen in the Raman spectrum. Strong frequency dispersion is found in the capacitance-voltage measurement. Normalized dielectric constant measurement is quantitatively utilized to characterize the dielectric constant variation. The relationship extracted between grain size and dielectric relaxation for CeO2 suggests that tuning properties for improved frequency dispersion can be achieved by controlling the grain size, hence the strain at the nanoscale dimensions.

Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements

In capacitance-voltage (C-V) measurements, frequency dispersion in high-k dielectrics is often observed. The frequency dependence of the dielectric constant (k-value), that is the intrinsic frequency dispersion, could not be assessed before suppressing the effects of extrinsic frequency dispersion, such as the effects of the lossy interfacial layer (between the high-k thin film and silicon substrate) and the parasitic effects. The effect of the lossy interfacial layer on frequency dispersion was investigated and modeled based on a dual frequency technique. The significance of parasitic effects (including series resistance and the back metal contact of the metal-oxide-semiconductor (MOS) capacitor) on frequency dispersion was also studied. The effect of surface roughness on frequency dispersion is also discussed. After taking extrinsic frequency dispersion into account, the relaxation behavior can be modeled using the Curie-von Schweidler (CS) law, the Kohlrausch-Williams-Watts (KWW) relationship and the Havriliak-Negami (HN) relationship. Dielectric relaxation mechanisms are also discussed.