FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method)

Dual-domain faster Fourier convolution based network for MR image reconstruction

Deep learning methods for fast MRI have shown promise in reconstructing high-quality images from undersampled multi-coil k-space data, leading to reduced scan duration. However, existing methods encounter challenges related to limited receptive fields in dual-domain (k-space and image domains) reconstruction networks, rigid data consistency operations, and suboptimal refinement structures, which collectively restrict overall reconstruction performance. This study introduces a comprehensive framework that addresses these challenges and enhances MR image reconstruction quality. Firstly, we propose Faster Inverse Fourier Convolution (FasterIFC), a frequency domain convolutional operator that significantly expands the receptive field of k-space domain reconstruction networks. Expanding the information extraction range to the entire frequency spectrum according to the spectral convolution theorem in Fourier theory enables the network to easily utilize richer redundant long-range information from adjacent, symmetrical, and diagonal locations of multi-coil k-space data. Secondly, we introduce a novel softer Data Consistency (softerDC) layer, which achieves an enhanced balance between data consistency and smoothness. This layer facilitates the implementation of diverse data consistency strategies across distinct frequency positions, addressing the inflexibility observed in current methods. Finally, we present the Dual-Domain Faster Fourier Convolution Based Network (D2F2), which features a centrosymmetric dual-domain parallel structure based on FasterIFC. This architecture optimally leverages dual-domain data characteristics while substantially expanding the receptive field in both domains. Coupled with the softerDC layer, D2F2 demonstrates superior performance on the NYU fastMRI dataset at multiple acceleration factors, surpassing state-of-the-art methods in both quantitative and qualitative evaluations.

FPGA Implementation of Image Registration Using Accelerated CNN

BACKGROUND

Accurate and fast image registration (IR) is critical during surgical interventions where the ultrasound (US) modality is used for image-guided intervention. Convolutional neural network (CNN)-based IR methods have resulted in applications that respond faster than traditional iterative IR methods. However, general-purpose processors are unable to operate at the maximum speed possible for real-time CNN algorithms. Due to its reconfigurable structure and low power consumption, the field programmable gate array (FPGA) has gained prominence for accelerating the inference phase of CNN applications.

METHODS

This study proposes an FPGA-based ultrasound IR CNN (FUIR-CNN) to regress three rigid registration parameters from image pairs. To speed up the estimation process, the proposed design makes use of fixed-point data and parallel operations carried out by unrolling and pipelining techniques. Experiments were performed on three US datasets in real time using the xc7z020, and the xcku5p was also used during implementation.

RESULTS

The FUIR-CNN produced results for the inference phase 139 times faster than the software-based network while retaining a negligible drop in regression performance of under 200 MHz clock frequency.

CONCLUSIONS

Comprehensive experimental results demonstrate that the proposed end-to-end FPGA-based accelerated CNN achieves a negligible loss, a high speed for registration parameters, less power when compared to the CPU, and the potential for real-time medical imaging.

Accelerating GRAPPA reconstruction using SoC design for real-time cardiac MRI

Real-time cardiac MRI is a rapidly developing area of research that has the potential to improve the diagnosis and treatment of cardiovascular diseases. However, the acquisition of high-quality real-time cardiac MR (CMR) images is challenging as it requires a high frame rate and temporal resolution. To overcome this challenge, there have been recent efforts on several approaches including hardware-based improvements and image reconstruction techniques such as compressed sensing and parallel MRI. The use of parallel MRI techniques such as GRAPPA (Generalized Autocalibrating Partial Parallel Acquisition) is a promising approach for improving the temporal resolution of MRI and expanding its applications in clinical practice. However, the GRAPPA algorithm involves a significant amount of computation, particularly for high acceleration factors and large datasets. This can result in long reconstruction times, which can limit the ability to achieve real-time imaging or high frame rates. One solution to this challenge is to use specialized hardware i.e. field-programmable gate arrays (FPGAs). In this work, a novel 32-bit floating-point FPGA-based GRAPPA accelerator is proposed with an aim to reconstruct high-quality cardiac MR images at higher frame rates, making it well suited for real-time clinical applications. The proposed FPGA-based accelerator consists of custom-designed data processing units named as dedicated computational engines (DCEs) that allow for a continuous flow of data between the calibration and synthesis stages of GRAPPA reconstruction process. This greatly increases the throughput and reduces the latency of the overall proposed system. Moreover, a high-speed memory module (DDR4-SDRAM) is integrated with the proposed architecture to store the multi-coil MR data. An on-chip quad-core ARM Cortex-A53 processor is used to manage access control information required for data transfer between the DCEs and DDR4-SDRAM. The proposed accelerator is implemented on Xilinx Zynq UltraScale + MPSoC using high-level synthesis (HLS) and hardware descriptive language (HDL) with an aim to explore the trade-offs between the reconstruction time, resource utilization and design effort. Several experiments have been performed using in-vivo cardiac datasets i.e. 18-receiver coil and 30-receiver coil to evaluate the performance of the proposed accelerator. A comparison is performed with the contemporary CPU and GPU-based GRAPPA reconstruction methods in terms of reconstruction time, frames-per-second and reconstruction accuracy (RMSE and SNR). The results show that the proposed accelerator achieves speed-up factors up to 121× and 9× as compared to the contemporary CPU-based and GPU-based GRAPPA reconstruction methods, respectively. Moreover, it has been demonstrated that the proposed accelerator can achieve reconstruction rates of up to ∼27 frames-per-second while maintaining the visual quality of the reconstructed images.

Hardware Architectures for Real-Time Medical Imaging

Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of patients. Earlier prediction and treatment have been driving the acquisition of higher image resolutions as well as the fusion of different modalities, raising the need for sophisticated hardware and software systems for medical image registration, storage, analysis, and processing. In this scenario and given the new clinical pipelines and the huge clinical burden of hospitals, these systems are often required to provide both highly accurate and real-time processing of large amounts of imaging data. Additionally, lowering the prices of each part of imaging equipment, as well as its development and implementation, and increasing their lifespan is crucial to minimize the cost and lead to more accessible healthcare. This paper focuses on the evolution and the application of different hardware architectures (namely, CPU, GPU, DSP, FPGA, and ASIC) in medical imaging through various specific examples and discussing different options depending on the specific application. The main purpose is to provide a general introduction to hardware acceleration techniques for medical imaging researchers and developers who need to accelerate their implementations.