Design of an MR image processing module on an FPGA chip

Hardware Architectures for Real-Time Medical Imaging

Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of patients. Earlier prediction and treatment have been driving the acquisition of higher image resolutions as well as the fusion of different modalities, raising the need for sophisticated hardware and software systems for medical image registration, storage, analysis, and processing. In this scenario and given the new clinical pipelines and the huge clinical burden of hospitals, these systems are often required to provide both highly accurate and real-time processing of large amounts of imaging data. Additionally, lowering the prices of each part of imaging equipment, as well as its development and implementation, and increasing their lifespan is crucial to minimize the cost and lead to more accessible healthcare. This paper focuses on the evolution and the application of different hardware architectures (namely, CPU, GPU, DSP, FPGA, and ASIC) in medical imaging through various specific examples and discussing different options depending on the specific application. The main purpose is to provide a general introduction to hardware acceleration techniques for medical imaging researchers and developers who need to accelerate their implementations.

ASIC modelling of SENSE for parallel MRI

Magnetic Resonance Imaging (MRI) is widely used in medical diagnostics and image reconstruction is a vital part of MRI systems. In Parallel MRI (pMRI), imaging process is accelerated by acquiring less data (undersampled) using multiple receiver coils and offline reconstruction algorithms are applied to reconstruct the fully sampled image. In this research, an Application Specific Integrated Circuits (ASIC) model of SENSE (a pMRI algorithm) is presented which reconstructs the image from the undersampled data right on the data acquisition module of the scanner. The proposed ASIC HDL architecture is compared with SENSE reconstruction model implemented on FPGAs, Multi-core CPU and Graphics Processing Units. The proposed architecture is validated using simulated brain data with 8-channel receiver coils and a human cardiac dataset with 20-channel receiver coils. The quality of the reconstructed images is analyzed using Artifact Power (0.0098), Peak Signal-to-Noise Ratio (53.4) and Structured Similarity Index (0.871) which validate the quality of the reconstructed images using the proposed design. The results show that the proposed ASIC HDL SENSE reconstruction model is ∼8000 times faster as compared to the multi-core CPU reconstruction, ∼700 times faster than the GPU implementation and ∼16 times faster as compared to the FPGA reconstruction model. The proposed architecture is suitable for image reconstruction right on the data acquisition system of the scanner and will open new ways for faster image reconstruction on portable MRI scanners.

Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

We report the design and implementation of a parallel two-dimensional fast Fourier transform (2D FFT) algorithm on a Field Programmable Gate Array (FPGA) for real-time MR image processing. Although a number of architectures of 2D FFT hardware processors have been reported, these generic processors or IP cores are not always effective for processing MRI data. The key feature of our design is that our processors are customized solely for real-time MRI applications. We demonstrate that by considering the unique features of real-time MRI data streams, we were able to develop and implement the 2D FFT processors that are resource-efficient and flexible enough to handle both regular and irregular data. Using a data-driven approach, we were able to simplify the inter-processor data communication while maintaining data synchronization without a synchronous clock signal bus and complex interconnection network. We experimentally verified our designs by processing multi-slice image data sets with 128 × 128 and 256 × 256 in-plane resolution. The results demonstrate the effectiveness of our 2D FFT processors and show that image reconstruction can be accelerated in proportion to the parallel processing factor. We achieved image-reconstruction processing rates up to 3000 and 800 slices per second for images with 128 × 128 and 256 × 256 in-plane resolution, respectively. The results also indicate that the image-reconstruction acceleration is primarily limited by the speed of the data transfer between the FPGA device and external sensors.

FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method

In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, "feature-motion decorrelation" still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these methods is the high computational complexity. Even the graphics processing unit (GPU)-based program requires a long time to finish the analysis. In this paper, we propose field-programmable gate array (FPGA)-based implementations of both methods for further acceleration. The capability of FPGAs on handling different image processing components in these methods is discussed. A fast and memory-saving image warping approach is proposed. The algorithms are reformulated to build a highly efficient pipeline on FPGA. The final implementations on a Xilinx Virtex-7 FPGA are at least 13 times faster than the GPU implementation on the NVIDIA graphic card (GeForce GTX 580).

Modularized architecture of address generation units suitable for real-time processing MR data on an FPGA

In this paper, we describe a modular approach to the design of an Address Generation Unit (AGU). The approach consists of development of a generic Address Generation Core (AGC) as a basic building block and the construction of an AGU from the AGCs. We illustrate this concept with AGUs capable of handling 2D- and 3D-structured data, and as well as their setup for executing 2D and 3D FFT algorithms on a Field Programmable Gate Array (FPGA). The AGUs developed using our proposed method are simple and easily expandable. Furthermore, they can potentially support irregularly structured data which are often generated from the wide variety of pulse sequences in magnetic resonance imaging. Our experimental results show that these AGUs are capable of generating addresses with a user-predefined pattern automatically at the speed of one address per clock cycle and operate at clock rates up to 80 MHz. They can operate concurrently with other processes and thus do not introduce additional operation latencies. Although we focus on applying the developed AGUs to executing 2D and 3D FFT, we expect that the modular design method should have much wider applications.