MemTorch: An Open-source Simulation Framework for Memristive Deep Learning Systems

Scalable Synaptic Transistor Memory from Solution-Processed Carbon Nanotubes for High-Speed Neuromorphic Data Processing

Neural networks as a core information processing technology in machine learning and artificial intelligence demand substantial computational resources to deal with the extensive multiply-accumulate operations. Neuromorphic computing is an emergent solution to address this problem, allowing the computation performed in memory arrays in parallel with high efficiencies conforming to the neural networks. Here, scalable synaptic transistor memories are developed from solution-sorted carbon nanotubes. The transistors exhibit a large switching ratio of over 105, a significant memory window of ≈12 V arising from charge trapping, and low response delays down to tens of nanoseconds. These device characteristics endow highly stabilized reconfigurable conductance states, successful emulation of synaptic functions, and a high data processing speed. Importantly, the devices exhibit uniform characteristic metrics, e.g., with a 1.8% variation in the memory window, suggesting an industrial-scale manufacturing capability of the fabrication. Using the memories, a hardware convolution kernel is designed and parallel image processing is demonstrated at a speed of 1 M bit per second per input channel. Given the efficacy of the convolution kernel, a promising prospect of the memories in implementing neuromorphic computing is envisaged. To explore the potential, large-scale convolution kernels are simulated and high-speed video processing is realized for autonomous driving.

A flexible and fast digital twin for RRAM systems applied for training resilient neural networks

Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).

Seizure Detection and Prediction by Parallel Memristive Convolutional Neural Networks

During the past two decades, epileptic seizure detection and prediction algorithms have evolved rapidly. However, despite significant performance improvements, their hardware implementation using conventional technologies, such as Complementary Metal-Oxide-Semiconductor (CMOS), in power and area-constrained settings remains a challenging task; especially when many recording channels are used. In this paper, we propose a novel low-latency parallel Convolutional Neural Network (CNN) architecture that has between 2-2,800x fewer network parameters compared to State-Of-The-Art (SOTA) CNN architectures and achieves 5-fold cross validation accuracy of 99.84% for epileptic seizure detection, and 99.01% and 97.54% for epileptic seizure prediction, when evaluated using the University of Bonn Electroencephalogram (EEG), CHB-MIT and SWEC-ETHZ seizure datasets, respectively. We subsequently implement our network onto analog crossbar arrays comprising Resistive Random-Access Memory (RRAM) devices, and provide a comprehensive benchmark by simulating, laying out, and determining hardware requirements of the CNN component of our system. We parallelize the execution of convolution layer kernels on separate analog crossbars to enable 2 orders of magnitude reduction in latency compared to SOTA hybrid Memristive-CMOS Deep Learning (DL) accelerators. Furthermore, we investigate the effects of non-idealities on our system and investigate Quantization Aware Training (QAT) to mitigate the performance degradation due to low Analog-to-Digital Converter (ADC)/Digital-to-Analog Converter (DAC) resolution. Finally, we propose a stuck weight offsetting methodology to mitigate performance degradation due to stuck [Formula: see text] memristor weights, recovering up to 32% accuracy, without requiring retraining. The CNN component of our platform is estimated to consume approximately 2.791 W of power while occupying an area of 31.255 mm² in a 22 nm FDSOI CMOS process.