Dielectric Engineered Two-Dimensional Neuromorphic Transistors

Lateral heterostructures of WS2 and MoS2 monolayers for photo-synaptic transistor

Von Neumann architecture-based computing, while widely successful in personal computers and embedded systems, faces inherent challenges including the von Neumann bottleneck, particularly amidst the ongoing surge of data-intensive tasks. Neuromorphic computing, designed to integrate arithmetic, logic, and memory operations, has emerged as a promising solution for improving energy efficiency and performance. This approach requires the construction of an artificial synaptic device that can simultaneously perform signal processing, learning, and memory operations. We present a photo-synaptic device with 32 analog multi-states by exploiting field-effect transistors based on the lateral heterostructures of two-dimensional (2D) WS2 and MoS2 monolayers, formed through a two-step metal-organic chemical vapor deposition process. These lateral heterostructures offer high photoresponsivity and enhanced efficiency of charge trapping at the interface between the heterostructures and SiO2 due to the presence of the WS2 monolayer with large trap densities. As a result, it enables the photo-synaptic transistor to implement synaptic behaviors of long-term plasticity and high recognition accuracy. To confirm the feasibility of the photo-synapse, we investigated its synaptic characteristics under optical and electrical stimuli, including the retention of excitatory post-synaptic currents, potentiation, habituation, nonlinearity factor, and paired-pulse facilitation. Our findings suggest the potential of versatile 2D material-synapse with a high density of device integration.

The Nonvolatile Memory and Neuromorphic Simulation of ReS2 /h-BN/Graphene Floating Gate Devices Under Photoelectrical Hybrid Modulations

The floating gate devices, as a kind of nonvolatile memory, obtain great application potential in logic-in-memory chips. The 2D materials have been greatly studied due to atomically flat surfaces, higher carrier mobility, and excellent photoelectrical response. The 2D ReS2 flake is an excellent candidate for channel materials due to thickness-independent direct bandgap and outstanding optoelectronic response. In this paper, the floating gate devices are prepared with the ReS2 /h-BN/Gr heterojunction. It obtains superior nonvolatile electrical memory characteristics, including a higher memory window ratio (81.82%), tiny writing/erasing voltage (±8 V/2 ms), long retention (>1000 s), and stable endurance (>1000 times) as well as multiple memory states. Meanwhile, electrical writing and optical erasing are achieved by applying electrical and optical pulses, and multilevel storage can easily be achieved by regulating light pulse parameters. Finally, due to the ideal long-time potentiation/depression synaptic weights regulated by light pulses and electrical pulses, the convolutional neural network (CNN) constructed by ReS2 /h-BN/Gr floating gate devices can achieve image recognition with an accuracy of up to 98.15% for MNIST dataset and 91.24% for Fashion-MNIST dataset. The research work adds a powerful option for 2D materials floating gate devices to apply to logic-in-memory chips and neuromorphic computing.

Non-volatile rippled-assisted optoelectronic array for all-day motion detection and recognition

In-sensor processing has the potential to reduce the energy consumption and hardware complexity of motion detection and recognition. However, the state-of-the-art all-in-one array integration technologies with simultaneous broadband spectrum image capture (sensory), image memory (storage) and image processing (computation) functions are still insufficient. Here, macroscale (2 × 2 mm2) integration of a rippled-assisted optoelectronic array (18 × 18 pixels) for all-day motion detection and recognition. The rippled-assisted optoelectronic array exhibits remarkable uniformity in the memory window, optically stimulated non-volatile positive and negative photoconductance. Importantly, the array achieves an extensive optical storage dynamic range exceeding 106, and exceptionally high room-temperature mobility up to 406.7 cm2 V-1 s-1, four times higher than the International Roadmap for Device and Systems 2028 target. Additionally, the spectral range of each rippled-assisted optoelectronic processor covers visible to near-infrared (405 nm-940 nm), achieving function of motion detection and recognition.

Polarized Tunneling Transistor for Ultralow-Energy-Consumption Artificial Synapse toward Neuromorphic Computing

Neural networks based on low-power artificial synapses can significantly reduce energy consumption, which is of great importance in today's era of artificial intelligence. Two-dimensional (2D) material-based floating-gate transistors (FGTs) have emerged as compelling candidates for simulating artificial synapses owing to their multilevel and nonvolatile data storage capabilities. However, the low erasing/programming speed of FGTs renders them unsuitable for low-energy-consumption artificial synapses, thereby limiting their potential in high-energy-efficient neuromorphic computing. Here, we introduce a FGT-inspired MoS2/Trap/PZT heterostructure-based polarized tunneling transistor (PTT) with a simple fabrication process and significantly enhanced erasing/programming speed. Distinct from the FGT, the PTT lacks a tunnel layer, leading to a marked improvement in its erasing/programming speed. The PTT's highest erasing/programming (operation) speed can reach ∼20 ns, which outperforms the performance of most FGTs based on 2D heterostructures. Furthermore, the PTT has been utilized as an artificial synapse, and its weight-update energy consumption can be as low as 0.0002 femtojoule (fJ), which benefits from the PTT's ultrahigh operation speed. Additionally, PTT-based artificial synapses have been employed in constructing artificial neural network simulations, achieving facial-recognition accuracy (95%). This groundbreaking work makes it possible for fabricating future high-energy-efficient neuromorphic transistors utilizing 2D materials.

PZT-Enabled MoS2 Floating Gate Transistors: Overcoming Boltzmann Tyranny and Achieving Ultralow Energy Consumption for High-Accuracy Neuromorphic Computing

Low-power electronic devices play a pivotal role in the burgeoning artificial intelligence era. The study of such devices encompasses low-subthreshold swing (SS) transistors and neuromorphic devices. However, conventional field-effect transistors (FETs) face the inherent limitation of the "Boltzmann tyranny", which restricts SS to 60 mV decade-1 at room temperature. Additionally, FET-based neuromorphic devices lack sufficient conductance states for highly accurate neuromorphic computing due to a narrow memory window. In this study, we propose a pioneering PZT-enabled MoS2 floating gate transistor (PFGT) configuration, demonstrating a low SS of 46 mV decade-1 and a wide memory window of 7.2 V in the dual-sweeping gate voltage range from -7 to 7 V. The wide memory window provides 112 distinct conductance states for PFGT. Moreover, the PFGT-based artificial neural network achieves an outstanding facial-recognition accuracy of 97.3%. This study lays the groundwork for the development of low-SS transistors and highly energy efficient artificial synapses utilizing two-dimensional materials.

Double-Floating-Gate van der Waals Transistor for High-Precision Synaptic Operations

Two-dimensional materials and their heterostructures have thus far been identified as leading candidates for nanoelectronics owing to the near-atom thickness, superior electrostatic control, and adjustable device architecture. These characteristics are indeed advantageous for neuro-inspired computing hardware where precise programming is strongly required. However, its successful demonstration fully utilizing all of the given benefits remains to be further developed. Herein, we present van der Waals (vdW) integrated synaptic transistors with multistacked floating gates, which are reconfigured upon surface oxidation. When compared with a conventional device structure with a single floating gate, our double-floating-gate (DFG) device exhibits better nonvolatile memory performance, including a large memory window (>100 V), high on-off current ratio (∼10⁷), relatively long retention time (>5000 s), and satisfactory cyclic endurance (>500 cycles), all of which can be attributed to its increased charge-storage capacity and spatial redistribution. This facilitates highly effective modulation of trapped charge density with a large dynamic range. Consequently, the DFG transistor exhibits an improved weight update profile in long-term potentiation/depression synaptic behavior for nearly ideal classification accuracies of up to 96.12% (MNIST) and 81.68% (Fashion-MNIST). Our work adds a powerful option to vdW-bonded device structures for highly efficient neuromorphic computing.

Nanopatterning Technologies of 2D Materials for Integrated Electronic and Optoelectronic Devices

With the reduction of feature size and increase of integration density, traditional 3D semiconductors are unable to meet the future requirements of chip integration. The current semiconductor fabrication technologies are approaching their physical limits based on Moore's law. 2D materials such as graphene, transitional metal dichalcogenides, etc., are of great promise for future memory, logic, and photonic devices due to their unique and excellent properties. To prompt 2D materials and devices from the laboratory research stage to the industrial integrated circuit-level, it is necessary to develop advanced nanopatterning methods to obtain high-quality, wafer-scale, and patterned 2D products. Herein, the recent development of nanopatterning technologies, particularly toward realizing large-scale practical application of 2D materials is reviewed. Based on the technological progress, the unique requirement and advances of the 2D integration process for logic, memory, and optoelectronic devices are further summarized. Finally, the opportunities and challenges of nanopatterning technologies of 2D materials for future integrated chip devices are prospected.

Quasi-two-dimensional α-molybdenum oxide thin film prepared by magnetron sputtering for neuromorphic computing

Two-dimensional (2D) layered materials have attracted intensive attention in recent years due to their rich physical properties, and shown great promise due to their low power consumption and high integration density in integrated electronics. However, mostly limited to mechanical exfoliation, large scale preparation of the 2D materials for application is still challenging. Herein, quasi-2D α-molybdenum oxide (α-MoO3) thin film with an area larger than 100 cm2 was fabricated by magnetron sputtering, which is compatible with modern semiconductor industry. An all-solid-state synaptic transistor based on this α-MoO3 thin film is designed and fabricated. Interestingly, by proton intercalation/deintercalation, the α-MoO3 channel shows a reversible conductance modulation of about four orders. Several indispensable synaptic behaviors, such as potentiation/depression and short-term/long-term plasticity, are successfully demonstrated in this synaptic device. In addition, multilevel data storage has been achieved. Supervised pattern recognition with high recognition accuracy is demonstrated in a three-layer artificial neural network constructed on this α-MoO3 based synaptic transistor. This work can pave the way for large scale production of the α-MoO3 thin film for practical application in intelligent devices.

Energy-Efficient III-V Tunnel FET-Based Synaptic Device with Enhanced Charge Trapping Ability Utilizing Both Hot Hole and Hot Electron Injections for Analog Neuromorphic Computing

A charge trap device based on field-effect transistors (FET) is a promising candidate for artificial synapses because of its high reliability and mature fabrication technology. However, conventional MOSFET-based charge trap synapses require a strong stimulus for synaptic update because of their inefficient hot-carrier injection into the charge trapping layer, consequently causing a slow speed operation and large power consumption. Here, we propose a highly efficient charge trap synapse using III-V materials-based tunnel field-effect transistor (TFET). Our synaptic TFETs present superior subthreshold swing and improved charge trapping ability utilizing both carriers as charge trapping sources: hot holes created by impact ionization in the narrow bandgap InGaAs after being provided from the p⁺-source, and band-to-band tunneling hot electrons (BBHEs) generated at the abrupt p⁺n junctions in the TFETs. Thanks to these advances, our devices achieved outstanding efficiency in synaptic characteristics with a 5750 times faster synaptic update speed and 51 times lower sub-fJ/um² energy consumption per single synaptic update in comparison to the MOSFET-based synapse. An artificial neural network (ANN) simulation also confirmed a high recognition accuracy of handwritten digits up to ∼90% in a multilayer perceptron neural network based on our synaptic devices.

Design of Functionally Stacked Channels of Oxide Thin-Film Transistors to Mimic Precise Ultralow-Light-Irradiated Synaptic Weight Modulation

To utilize continuous ultralow intensity signals from oxide synaptic transistors as artificial synapses that mimic human visual perception, we propose strategic oxide channels that optimally utilize their advantageous functions by stacking two oxide semiconductors with different conductivities. The bottom amorphous indium–gallium–zinc oxide (a-IGZO) layer with a relatively low conductivity was designed for an extremely low initial postsynaptic current (PSCi) by achieving full depletion at a low negative gate voltage, and the stacked top amorphous indium–zinc oxide (a-IZO) layer improved the amplitude of the synaptic current and memory retention owing to the enhancement in the persistent photoconductivity characteristics. We demonstrated an excellent photonic synapse thin-film transistor (TFT) with a precise synaptic weight change even in the range of ultralow light intensity by adapting this stacking IGZO/IZO channel. The proposed device exhibited distinct ∆PSC values of 3.1 and 18.1 nA under ultralow ultraviolet light (350 nm, 50 ms) of 1.6 and 8.0 μW/cm2. In addition, while the lowest light input exhibited short-term plasticity characteristics similar to the “volatile-like” behavior of the human brain with a current recovery close to the initial value, the increase in light intensity caused long-term plasticity characteristics, thus achieving synaptic memory transition in the IGZO/IZO TFTs.

Artificially created interfacial states enabled van der Waals heterostructure memory device

Two-dimensional (2D) interface plays a predominate role in determining the performance of a device that is configured as a van der Waals heterostructure (vdWH). Intensive efforts have been devoted to suppressing the emergence of interfacial states during vdWH stacking process, which facilitates the charge interaction and transfer between the heterostructure layers. However, the effective generation and modulation of the vdWH interfacial states could give rise to a new design and architecture of 2D functional devices. Here, we report a 2D non-volatile vdWH memory device enabled by the artificially created interfacial states between hexagonal boron nitride (hBN) and molybdenum ditelluride (MoTe₂). The memory originates from the microscopically coupled optical and electrical responses of the vdWH, with the high reliability reflected by its long data retention time over 10⁴s and large write-erase cyclic number exceeding 100. Moreover, the storage currents in the memory can be precisely controlled by the writing and erasing gates, demonstrating the tunability of its storage states. The vdWH memory also exhibits excellent robustness with wide temperature endurance window from 100 K to 380 K, illustrating its potential application in harsh environment. Our findings promise interfacial-states engineering as a powerful approach to realize high performance vdWH memory device, which opens up new opportunities for its application in 2D electronics and optoelectronics.