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Sleziona S, Pelella A, Faella E, Kharsah O, Skopinski L, Maas A, Liebsch Y, Schmeink J, Di Bartolomeo A, Schleberger M. Manipulation of the electrical and memory properties of MoS 2 field-effect transistors by highly charged ion irradiation. NANOSCALE ADVANCES 2023; 5:6958-6966. [PMID: 38059017 PMCID: PMC10696994 DOI: 10.1039/d3na00543g] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Grants] [Track Full Text] [Figures] [Subscribe] [Scholar Register] [Received: 07/20/2023] [Accepted: 10/24/2023] [Indexed: 12/08/2023]
Abstract
Field-effect transistors based on molybdenum disulfide (MoS2) exhibit a hysteresis in their transfer characteristics, which can be utilized to realize 2D memory devices. This hysteresis has been attributed to charge trapping due to adsorbates, or defects either in the MoS2 lattice or in the underlying substrate. We fabricated MoS2 field-effect transistors on SiO2/Si substrates, irradiated these devices with Xe30+ ions at a kinetic energy of 180 keV to deliberately introduce defects and studied the resulting changes of their electrical and hysteretic properties. We find clear influences of the irradiation: while the charge carrier mobility decreases linearly with increasing ion fluence (up to only 20% of its initial value) the conductivity actually increases again after an initial drop of around two orders of magnitude. We also find a significantly reduced n-doping (≈1012 cm-2) and a well-developed hysteresis after the irradiation. The hysteresis height increases with increasing ion fluence and enables us to characterize the irradiated MoS2 field-effect transistor as a memory device with remarkably longer relaxation times (≈ minutes) compared to previous works.
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Affiliation(s)
- Stephan Sleziona
- Faculty of Physics and CENIDE, University of Duisburg-Essen Lotharstraße 1 D-47057 Duisburg Germany
| | - Aniello Pelella
- Department of Physics "E. R. Caianiello", University of Salerno, and CNR-SPIN via Giovanni Paolo II Fisciano 84084 Salerno Italy
| | - Enver Faella
- Department of Physics "E. R. Caianiello", University of Salerno, and CNR-SPIN via Giovanni Paolo II Fisciano 84084 Salerno Italy
| | - Osamah Kharsah
- Faculty of Physics and CENIDE, University of Duisburg-Essen Lotharstraße 1 D-47057 Duisburg Germany
| | - Lucia Skopinski
- Faculty of Physics and CENIDE, University of Duisburg-Essen Lotharstraße 1 D-47057 Duisburg Germany
| | - André Maas
- Faculty of Physics and CENIDE, University of Duisburg-Essen Lotharstraße 1 D-47057 Duisburg Germany
| | - Yossarian Liebsch
- Faculty of Physics and CENIDE, University of Duisburg-Essen Lotharstraße 1 D-47057 Duisburg Germany
| | - Jennifer Schmeink
- Faculty of Physics and CENIDE, University of Duisburg-Essen Lotharstraße 1 D-47057 Duisburg Germany
| | - Antonio Di Bartolomeo
- Department of Physics "E. R. Caianiello", University of Salerno, and CNR-SPIN via Giovanni Paolo II Fisciano 84084 Salerno Italy
| | - Marika Schleberger
- Faculty of Physics and CENIDE, University of Duisburg-Essen Lotharstraße 1 D-47057 Duisburg Germany
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2
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Mallik SK, Padhan R, Sahu MC, Roy S, Pradhan GK, Sahoo PK, Dash SP, Sahoo S. Thermally Driven Multilevel Non-Volatile Memory with Monolayer MoS 2 for Brain-Inspired Artificial Learning. ACS APPLIED MATERIALS & INTERFACES 2023. [PMID: 37467425 DOI: 10.1021/acsami.3c06336] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 07/21/2023]
Abstract
The demands of modern electronic components require advanced computing platforms for efficient information processing to realize in-memory operations with a high density of data storage capabilities toward developing alternatives to von Neumann architectures. Herein, we demonstrate the multifunctionality of monolayer MoS2 memtransistors, which can be used as a high-geared intrinsic transistor at room temperature; however, at a high temperature (>350 K), they exhibit synaptic multilevel memory operations. The temperature-dependent memory mechanism is governed by interfacial physics, which solely depends on the gate field modulated ion dynamics and charge transfer at the MoS2/dielectric interface. We have proposed a non-volatile memory application using a single Field Effect Transistor (FET) device where thermal energy can be ventured to aid the memory functions with multilevel (3-bit) storage capabilities. Furthermore, our devices exhibit linear and symmetry in conductance weight updates when subjected to electrical potentiation and depression. This feature has enabled us to attain a high classification accuracy while training and testing the Modified National Institute of Standards and Technology datasets through artificial neural network simulation. This work paves the way toward reliable data processing and storage using 2D semiconductors with high-packing density arrays for brain-inspired artificial learning.
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Affiliation(s)
- Sameer Kumar Mallik
- Laboratory for Low Dimensional Materials, Institute of Physics, Bhubaneswar 751005, India
- Homi Bhabha National Institute, Training School Complex, Anushakti Nagar, Mumbai 400094, India
| | - Roshan Padhan
- Laboratory for Low Dimensional Materials, Institute of Physics, Bhubaneswar 751005, India
- Homi Bhabha National Institute, Training School Complex, Anushakti Nagar, Mumbai 400094, India
| | - Mousam Charan Sahu
- Laboratory for Low Dimensional Materials, Institute of Physics, Bhubaneswar 751005, India
- Homi Bhabha National Institute, Training School Complex, Anushakti Nagar, Mumbai 400094, India
| | - Suman Roy
- Laboratory for Low Dimensional Materials, Institute of Physics, Bhubaneswar 751005, India
- Homi Bhabha National Institute, Training School Complex, Anushakti Nagar, Mumbai 400094, India
| | - Gopal K Pradhan
- Department of Physics, School of Applied Sciences, KIIT Deemed to be University, Bhubaneswar 751024, Odisha, India
| | - Prasana Kumar Sahoo
- Materials Science Centre, Quantum Materials and Device Research Laboratory, Indian Institute of Technology Kharagpur, Kharagpur 721302, West Bengal, India
| | - Saroj Prasad Dash
- Quantum Device Physics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg 41296, Sweden
| | - Satyaprakash Sahoo
- Laboratory for Low Dimensional Materials, Institute of Physics, Bhubaneswar 751005, India
- Homi Bhabha National Institute, Training School Complex, Anushakti Nagar, Mumbai 400094, India
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3
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Kim MS, Choi DH, Lee IH, Kim WS, Kwon D, Bae MH, Kim JJ. Gate-voltage-induced reversible electrical phase transitions in Mo 0.67W 0.33Se 2 devices. NANOSCALE 2022; 14:16611-16617. [PMID: 36317650 DOI: 10.1039/d2nr04311d] [Citation(s) in RCA: 2] [Impact Index Per Article: 1.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/16/2023]
Abstract
Tunable electrical phase transitions based on the structural and quantum-state phase transitions in two-dimensional transition-metal dichalcogenides have attracted attention in both semiconducting electronics and quantum electronics applications. Here, we report gate-voltage-induced reversible electrical phase transitions in Mo0.67W0.33Se2 (MoWSe) field-effect transistors prepared on SiO2/Si substrates. In gate-induced depletion regions of the 2H phase, an electrical current resumes flow at 150 K < T < 200 K with decreasing T irrespective of the layer number (n) for MoWSe when n < 20. The newly appearing electron-doped-type conducting channel again enters the 2H-phase region when the back-gate voltage increases, accompanied by the negative differential transconductance for four-layer and monolayer devices or by a deflection point in the transfer curves for a multilayer device. The thermal activation energies of the new conducting and 2H-phase branches differ by one order of magnitude at the same gate voltage for both the four-layer and monolayer cases, indicating that the electrical band at the Fermi level was modified. The hysteresis measurements for the gate voltage were performed with a five-layer device, which confirms the reversible electrical transition behavior. The possible origins of the nucleated conducting phase in the depletion region of the 2H phase of MoWSe are discussed.
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Affiliation(s)
- Min-Sik Kim
- Department of Physics, Jeonbuk National University, Jeonju 54896, Republic of Korea.
- Korea Research Institute of Standards and Science, Daejeon 34113, Republic of Korea.
| | - Dong-Hwan Choi
- Department of Physics, Jeonbuk National University, Jeonju 54896, Republic of Korea.
- Korea Research Institute of Standards and Science, Daejeon 34113, Republic of Korea.
| | - In-Ho Lee
- Korea Research Institute of Standards and Science, Daejeon 34113, Republic of Korea.
| | - Wu-Sin Kim
- Department of Physics, Jeonbuk National University, Jeonju 54896, Republic of Korea.
| | - Duhyuk Kwon
- Korea Research Institute of Standards and Science, Daejeon 34113, Republic of Korea.
- Department of Physics, Chungnam National University, Daejeon 34134, Republic of Korea
| | - Myung-Ho Bae
- Korea Research Institute of Standards and Science, Daejeon 34113, Republic of Korea.
- Department of Nano Science, University of Science and Technology, Daejeon, 34113, Republic of Korea
| | - Ju-Jin Kim
- Department of Physics, Jeonbuk National University, Jeonju 54896, Republic of Korea.
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Gao M, Wei W, Han T, Li B, Zeng Z, Luo L, Zhu C. Defect Engineering in Thickness-Controlled Bi 2O 2Se-Based Transistors by Argon Plasma Treatment. ACS APPLIED MATERIALS & INTERFACES 2022; 14:15370-15380. [PMID: 35319194 DOI: 10.1021/acsami.1c24260] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/14/2023]
Abstract
We present a simple, effective, and controllable method to uniformly thin down the thickness of as-exfoliated two-dimensional Bi2O2Se nanoflakes using Ar+ plasma treatment. Atomic force microscopy (AFM) images and Raman spectra indicate that the surface morphology and crystalline quality of etched Bi2O2Se nanoflakes remain almost unaffected. X-ray photoelectron spectra (XPS) indicate that the O and Se vacancies created during Ar+ plasma etching on the top surface of Bi2O2Se nanoflakes are passivated by forming an ultrathin oxide layer with UV O3 treatment. Moreover, a bottom-gate Bi2O2Se-based field-effect transistor (FET) was constructed to research the effect of thicknesses and defects on electronic properties. The on-current/off-current (Ion/Ioff) ratio of the Bi2O2Se FET increases with decreasing Bi2O2Se thickness and is further improved by UV O3 treatment. Eventually, the thickness-controlled Bi2O2Se FET achieves a high Ion/Ioff ratio of 6.0 × 104 and a high field-effect mobility of 5.7 cm2 V-1 s-1. Specifically, the variation trend of the Ion/Ioff ratio and the electronic transport properties for the bottom-gate Bi2O2Se-based FET are well described by a parallel resistor model (including bulk, channel, and defect resistance). Furthermore, the Ids-Vgs hysteresis and its inversion with UV irradiation were observed. The pulsed gate and drain voltage measurements were used to extract trap time constants and analyze the formation mechanism of different hysteresis. Before UV irradiation, the origin of clockwise hysteresis is attributed to the charge trapping/detrapping of defects at the Bi2O2Se/SiO2 interface and in the Bi2O2Se bulk. After UV irradiation, the large anticlockwise hysteresis is mainly due to the tunneling between deep-level oxygen defects in SiO2 and p++-Si gate, which implies the potential in nonvolatile memory.
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Affiliation(s)
- Ming Gao
- Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, 117583 Singapore
| | - Wei Wei
- Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, 117583 Singapore
| | - Tao Han
- Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, 117583 Singapore
- School of Microelectronics, Xidian University, Xi'an 710071, China
| | - Bochang Li
- Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, 117583 Singapore
| | - Zhe Zeng
- Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, 117583 Singapore
| | - Li Luo
- Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, 117583 Singapore
- College of Electronic and Information Engineering, Southwest University, Chongqing 400715, China
| | - Chunxiang Zhu
- Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, 117583 Singapore
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5
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Nguyen DA, Jo Y, Tran TU, Jeong MS, Kim H, Im H. Electrically and Optically Controllable p-n Junction Memtransistor Based on an Al 2 O 3 Encapsulated 2D Te/ReS 2 van der Waals Heterostructure. SMALL METHODS 2021; 5:e2101303. [PMID: 34928036 DOI: 10.1002/smtd.202101303] [Citation(s) in RCA: 5] [Impact Index Per Article: 1.7] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 10/17/2021] [Indexed: 06/14/2023]
Abstract
The exploration of memtransistors as a combination of a memristor and a transistor has recently attracted intensive attention because it offers a promising candidate for next-generation multilevel nonvolatile memories and synaptic devices. However, the present state-of-the-art memtransistors, which are based on a single material, such as MoS2 or perovskite, exhibit a relatively low switching ratio, require extremely high electric fields to modulate bistable resistance states and do not perform multifunctional operations. Here, the realization of an electrically and optically controllable p-n junction memtransistor using an Al2 O3 encapsulated 2D Te/ReS2 van der Waals heterostructure is reported. The hybrid memtransistor shows a reversible bipolar resistance switching behavior between a low resistance state and a high resistance state with a high switching ratio up to 106 at a low operating voltage (<10 V), high cycling endurance, and long retention time. Moreover, multiple resistance states are achieved by applying different bias voltages, gate voltages, or light powers. In addition, logical operations, including the inverter and AND/OR gates, and synaptic activities are performed by controlling the optical and electrical inputs. The work offers a novel strategy for the reliable fabrication of p-n junction memtransistors for multifunctional devices and neuromorphic applications.
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Affiliation(s)
- Duc Anh Nguyen
- Division of Physics and Semiconductor Science, Dongguk University, Seoul, 04620, Republic of Korea
| | - Yongcheol Jo
- Division of Physics and Semiconductor Science, Dongguk University, Seoul, 04620, Republic of Korea
| | - Thi Uyen Tran
- Department of Energy Science, Sungkyunkwan University, Suwon, 16419, Republic of Korea
| | - Mun Seok Jeong
- Department of Physics, Department of Energy Engineering, Hanyang University, Seoul, 04763, Republic of Korea
| | - Hyungsang Kim
- Division of Physics and Semiconductor Science, Dongguk University, Seoul, 04620, Republic of Korea
| | - Hyunsik Im
- Division of Physics and Semiconductor Science, Dongguk University, Seoul, 04620, Republic of Korea
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Yin L, Cheng R, Wen Y, Liu C, He J. Emerging 2D Memory Devices for In-Memory Computing. ADVANCED MATERIALS (DEERFIELD BEACH, FLA.) 2021; 33:e2007081. [PMID: 34105195 DOI: 10.1002/adma.202007081] [Citation(s) in RCA: 42] [Impact Index Per Article: 14.0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 10/17/2020] [Revised: 12/27/2020] [Indexed: 06/12/2023]
Abstract
It is predicted that the conventional von Neumann computing architecture cannot meet the demands of future data-intensive computing applications due to the bottleneck between the processing and memory units. To try to solve this problem, in-memory computing technology, where calculations are carried out in situ within each nonvolatile memory unit, has been intensively studied. Among various candidate materials, 2D layered materials have recently demonstrated many new features that have been uniquely exploited to build next-generation electronics. Here, the recent progress of 2D memory devices is reviewed for in-memory computing. For each memory configuration, their operation mechanisms and memory characteristics are described, and their pros and cons are weighed. Subsequently, their versatile applications for in-memory computing technology, including logic operations, electronic synapses, and random number generation are presented. Finally, the current challenges and potential strategies for future 2D in-memory computing systems are also discussed at the material, device, circuit, and architecture levels. It is hoped that this manuscript could give a comprehensive review of 2D memory devices and their applications in in-memory computing, and be helpful for this exciting research area.
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Affiliation(s)
- Lei Yin
- Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, and School of Physics and Technology, Wuhan University, Wuhan, 430072, P. R. China
| | - Ruiqing Cheng
- Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, and School of Physics and Technology, Wuhan University, Wuhan, 430072, P. R. China
| | - Yao Wen
- Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, and School of Physics and Technology, Wuhan University, Wuhan, 430072, P. R. China
| | - Chuansheng Liu
- Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, and School of Physics and Technology, Wuhan University, Wuhan, 430072, P. R. China
| | - Jun He
- Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, and School of Physics and Technology, Wuhan University, Wuhan, 430072, P. R. China
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7
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Jawa H, Varghese A, Lodha S. Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS 2 Field-Effect Transistors. ACS APPLIED MATERIALS & INTERFACES 2021; 13:9186-9194. [PMID: 33555851 DOI: 10.1021/acsami.0c21530] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/12/2023]
Abstract
Clockwise to anticlockwise hysteresis crossover in current-voltage transfer characteristics of field-effect transistors (FETs) with graphene and MoS2 channels holds significant promise for nonvolatile memory applications. However, such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS2 FETs using a gate-drain underlap design to induce a differential response from traps near the MoS2-HfO2 channel-gate dielectric interface, also referred to as border traps, to applied gate bias. The appearance of trap-driven anticlockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS2 channel flake. The underlap design also enables room temperature tuning of the anticlockwise hysteresis window (by 140×) as well as the crossover gate voltage (by 2.6×) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 °C, and 65 °C) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO2 traps to the clockwise and anticlockwise hysteresis.
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Affiliation(s)
- Himani Jawa
- Department of Electrical Engineering, IIT Bombay, Mumbai, Maharashtra 400076, India
| | - Abin Varghese
- Department of Electrical Engineering, IIT Bombay, Mumbai, Maharashtra 400076, India
- Department of Materials Science and Engineering, Monash University, Clayton, Victoria 3800, Australia
| | - Saurabh Lodha
- Department of Electrical Engineering, IIT Bombay, Mumbai, Maharashtra 400076, India
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Lee K, Kim Y, Kim D, Lee J, Lee H, Joo MK, Cho YH, Shin J, Ji H, Kim GT. Metal-Contact Improvement in a Multilayer WSe 2 Transistor through Strong Hot Carrier Injection. ACS APPLIED MATERIALS & INTERFACES 2021; 13:2829-2835. [PMID: 33410320 DOI: 10.1021/acsami.0c18319] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/12/2023]
Abstract
Hot carrier injection (HCI), occurring when the horizontal electric field is strongly applied, usually affects the degradation of nanoelectronic devices. In addition, metal contacts play a significant role in nanoelectronic devices. In this study, Schottky contacts in multilayer tungsten diselenide (WSe2) field-effect transistors (FETs) by hot carrier injection (HCI), occurring when a high drain voltage is applied, is investigated. A small number of hot carriers with high energy reduces the Schottky barrier height and improves the performance of FETs effectively rather than damaging the channel. Thermal annealing at the end of the fabrication process increases device performance by causing interfacial reactions of the source/drain electrodes. HCI causes a significant enhancement in the local asymmetry, especially in the subthreshold region. The subthreshold swing (SS) of the thermally annealed FETs is significantly improved from 9.66 to 0.562 V dec-1 through the energy of HCI generated by a strong horizontal electric field. In addition, the contact resistances (RSD), also called series resistances, extracted by a four-probe measurement and a Y-function method were also improved by decreasing to a 10th through the energy of HCI. To understand the asymmetrical characteristics of the channel after the stress, we performed electrical analysis, electrostatic force microscopy (EFM), and Raman spectroscopy.
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Affiliation(s)
- Kookjin Lee
- IMEC, 3001 Leuven, Belgium
- Department of Materials Science, KU Leuven, 3001 Leuven, Belgium
- School of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea
| | - Yeonsu Kim
- School of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea
| | - Doyoon Kim
- School of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea
| | - Jaewoo Lee
- School of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea
| | - Hyebin Lee
- School of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea
- Samsung Electronics Co. Ltd., 1 Samsung-ro, Yongin-si, Gyeonggi-do 17113, Republic of Korea
| | - Min-Kyu Joo
- Department of Applied Physics, Sookmyung Women's University, Seoul 04310, Republic of Korea
| | - Young-Hoon Cho
- Samsung Electronics Co. Ltd., 1 Samsung-ro, Yongin-si, Gyeonggi-do 17113, Republic of Korea
| | - Jinwoo Shin
- Agency of Defense Development, Daejeon 305-600, Republic of Korea
| | - Hyunjin Ji
- School of Electrical Engineering, University of Ulsan, Ulsan 680-749, Republic of Korea
| | - Gyu-Tae Kim
- School of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea
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9
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Prasad P, Garg M, Chandni U. Tailoring the transfer characteristics and hysteresis in MoS 2 transistors using substrate engineering. NANOSCALE 2020; 12:23817-23823. [PMID: 33237076 DOI: 10.1039/d0nr05861k] [Citation(s) in RCA: 2] [Impact Index Per Article: 0.5] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/13/2023]
Abstract
We demonstrate a novel form of transfer characteristics in substrate engineered MoS2 field effect transistors. Robust hysteresis with stable threshold voltages and a large gate voltage window is observed, which is suppressed at low temperatures. We analyse the dependence of the device characteristics on gate voltage range, gate stressing and sweep rates. We infer that the hysteresis originates from artificially created charged traps near the MoS2-SiO2 interface. These charge traps act as long range Coulomb scatterers and are screened at high carrier densities. The hysteresis is strongly suppressed in measurements on wafers devoid of the substrate treatment, providing a new extrinsic route to carefully tune the transfer characteristics.
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Affiliation(s)
- Pragya Prasad
- Department of Instrumentation and Applied Physics, Indian Institute of Science, Bangalore 560012, India.
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10
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Lee K, Lee H, Kim Y, Choi J, Ahn JP, Shin DH, Cho YH, Jang HK, Lee SW, Shin J, Ji H, Kim GT. Real-time effect of electron beam on MoS 2 field-effect transistors. NANOTECHNOLOGY 2020; 31:455202. [PMID: 32325431 DOI: 10.1088/1361-6528/ab8c78] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/11/2023]
Abstract
Irradiation of MoS2 field-effect transistors (FETs) fabricated on Si/SiO2 substrates with electron beams (e-beams) below 30 keV creates electron-hole pairs (EHP) in the SiO2, which increase the interface trap density (Nit ) and change the current path in the channel, resulting in performance changes. In situ measurements of the electrical characteristics of the FET performed using a nano-probe system mounted inside a scanning electron microscope show that e-beam irradiation enables both multilayer and monolayer MoS2 channels act as conductors. The e-beams mostly penetrate the channel owing to their large kinetic energy, while the EHPs formed in the SiO2 layer can contribute to the conductance by flowing into the MoS2 channel or inducing the gate bias effect. The analysis of the device parameters in the initial state and the vent-evacuation state after e-beam irradiation can clarify the effect of the interplay between the e-beam-induced EHPs and ambient adsorbates on the carrier behavior, which depends on the thickness of the MoS2 layer. DC and low frequency noise analysis reveals that the e-beam-induced EHPs increase Nit from 109-1010 to 1011 cm-2 eV-1 in both monolayer and multilayer devices, while the interfacial Coulomb scattering parameter αSC increases by three times in the monolayer and decreases to one-tenth of its original value in the multilayer. In other words, an MoS2 layer with a thickness of ∼30 nm is less sensitive to adsorbates by surface screening. Thus, the carrier mobility in the monolayer device decreases from 45.7 to 40 cm2 V-1 s-1, while in the 30 nm-thick multilayer device, it increases from 4.9 to 5.6 cm2 V-1 s-1. This is further evidenced by simulations of the distribution of interface traps and channel carriers in the MoS2 FET before and after e-beam irradiation, demonstrating that Coulomb scattering decreases as the effective channel moves away from the interface.
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Affiliation(s)
- Kookjin Lee
- School of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul 02841, Republic of Korea
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Abstract
Two-dimensional (2D) layered materials and their heterostructures have recently been recognized as promising building blocks for futuristic brain-like neuromorphic computing devices. They exhibit unique properties such as near-atomic thickness, dangling-bond-free surfaces, high mechanical robustness, and electrical/optical tunability. Such attributes unattainable with traditional electronic materials are particularly promising for high-performance artificial neurons and synapses, enabling energy-efficient operation, high integration density, and excellent scalability. In this review, diverse 2D materials explored for neuromorphic applications, including graphene, transition metal dichalcogenides, hexagonal boron nitride, and black phosphorous, are comprehensively overviewed. Their promise for neuromorphic applications are fully discussed in terms of material property suitability and device operation principles. Furthermore, up-to-date demonstrations of neuromorphic devices based on 2D materials or their heterostructures are presented. Lastly, the challenges associated with the successful implementation of 2D materials into large-scale devices and their material quality control will be outlined along with the future prospect of these emergent materials.
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Sangwan VK, Hersam MC. Neuromorphic nanoelectronic materials. NATURE NANOTECHNOLOGY 2020; 15:517-528. [PMID: 32123381 DOI: 10.1038/s41565-020-0647-z] [Citation(s) in RCA: 205] [Impact Index Per Article: 51.3] [Reference Citation Analysis] [Abstract] [MESH Headings] [Track Full Text] [Subscribe] [Scholar Register] [Received: 07/09/2019] [Accepted: 01/23/2020] [Indexed: 05/10/2023]
Abstract
Memristive and nanoionic devices have recently emerged as leading candidates for neuromorphic computing architectures. While top-down fabrication based on conventional bulk materials has enabled many early neuromorphic devices and circuits, bottom-up approaches based on low-dimensional nanomaterials have shown novel device functionality that often better mimics a biological neuron. In addition, the chemical, structural and compositional tunability of low-dimensional nanomaterials coupled with the permutational flexibility enabled by van der Waals heterostructures offers significant opportunities for artificial neural networks. In this Review, we present a critical survey of emerging neuromorphic devices and architectures enabled by quantum dots, metal nanoparticles, polymers, nanotubes, nanowires, two-dimensional layered materials and van der Waals heterojunctions with a particular emphasis on bio-inspired device responses that are uniquely enabled by low-dimensional topology, quantum confinement and interfaces. We also provide a forward-looking perspective on the opportunities and challenges of neuromorphic nanoelectronic materials in comparison with more mature technologies based on traditional bulk electronic materials.
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Affiliation(s)
- Vinod K Sangwan
- Department of Materials Science and Engineering, Northwestern University, Evanston, IL, USA
| | - Mark C Hersam
- Department of Materials Science and Engineering, Northwestern University, Evanston, IL, USA.
- Department of Chemistry, Northwestern University, Evanston, IL, USA.
- Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, USA.
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13
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Yamamoto M, Nouchi R, Kanki T, Hattori AN, Watanabe K, Taniguchi T, Ueno K, Tanaka H. Gate-Tunable Thermal Metal-Insulator Transition in VO 2 Monolithically Integrated into a WSe 2 Field-Effect Transistor. ACS APPLIED MATERIALS & INTERFACES 2019; 11:3224-3230. [PMID: 30604604 DOI: 10.1021/acsami.8b18745] [Citation(s) in RCA: 7] [Impact Index Per Article: 1.4] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/09/2023]
Abstract
Vanadium dioxide (VO2) shows promise as a building block of switching and sensing devices because it undergoes an abrupt metal-insulator transition (MIT) near room temperature, where the electrical resistivity changes by orders of magnitude. A challenge for versatile applications of VO2 is to control the MIT by gating in the field-effect device geometry. Here, we demonstrate a gate-tunable abrupt switching device based on a VO2 microwire that is monolithically integrated with a two-dimensional (2D) tungsten diselenide (WSe2) semiconductor by van der Waals stacking. We fabricated the WSe2 transistor using the VO2 wire as the drain contact, titanium as the source contact, and hexagonal boron nitride as the gate dielectric. The WSe2 transistor was observed to show ambipolar transport, with higher conductivity in the electron branch. The electron current increases continuously with gate voltage below the critical temperature of the MIT of VO2. Near the critical temperature, the current shows an abrupt and discontinuous jump at a given gate voltage, indicating that the MIT in the contacting VO2 is thermally induced by gate-mediated self-heating. Our results have paved the way for the development of VO2-based gate-tunable devices by the van der Waals stacking of 2D semiconductors, with great potential for electronic and photonic applications.
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Affiliation(s)
- Mahito Yamamoto
- Institute of Scientific and Industrial Research , Osaka University , Ibaraki , Osaka 567-0047 , Japan
| | - Ryo Nouchi
- Graduate School of Engineering , Osaka Prefecture University , Sakai , Osaka 599-8570 , Japan
- JST PRESTO , Kawaguchi , Saitama 332-0012 , Japan
| | - Teruo Kanki
- Institute of Scientific and Industrial Research , Osaka University , Ibaraki , Osaka 567-0047 , Japan
| | - Azusa N Hattori
- Institute of Scientific and Industrial Research , Osaka University , Ibaraki , Osaka 567-0047 , Japan
- JST PRESTO , Kawaguchi , Saitama 332-0012 , Japan
| | - Kenji Watanabe
- National Institute for Materials Science , Tsukuba , Ibaraki 305-0044 , Japan
| | - Takashi Taniguchi
- National Institute for Materials Science , Tsukuba , Ibaraki 305-0044 , Japan
| | - Keiji Ueno
- Department of Chemistry, Graduate School of Science and Engineering , Saitama University , Saitama 338-8570 , Japan
| | - Hidekazu Tanaka
- Institute of Scientific and Industrial Research , Osaka University , Ibaraki , Osaka 567-0047 , Japan
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14
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Liu C, Yan X, Song X, Ding S, Zhang DW, Zhou P. A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications. NATURE NANOTECHNOLOGY 2018; 13:404-410. [PMID: 29632398 DOI: 10.1038/s41565-018-0102-6] [Citation(s) in RCA: 139] [Impact Index Per Article: 23.2] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Received: 03/18/2017] [Accepted: 02/21/2018] [Indexed: 05/09/2023]
Abstract
As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.
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Affiliation(s)
- Chunsen Liu
- State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China
| | - Xiao Yan
- State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China
| | - Xiongfei Song
- State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China
| | - Shijin Ding
- State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China
| | - David Wei Zhang
- State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China.
| | - Peng Zhou
- State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China.
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15
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Sangwan VK, Lee HS, Bergeron H, Balla I, Beck ME, Chen KS, Hersam MC. Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide. Nature 2018; 554:500-504. [DOI: 10.1038/nature25747] [Citation(s) in RCA: 494] [Impact Index Per Article: 82.3] [Reference Citation Analysis] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Received: 06/08/2017] [Accepted: 12/19/2017] [Indexed: 12/22/2022]
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16
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He G, Nathawat J, Kwan CP, Ramamoorthy H, Somphonsane R, Zhao M, Ghosh K, Singisetti U, Perea-López N, Zhou C, Elías AL, Terrones M, Gong Y, Zhang X, Vajtai R, Ajayan PM, Ferry DK, Bird JP. Negative Differential Conductance & Hot-Carrier Avalanching in Monolayer WS2 FETs. Sci Rep 2017; 7:11256. [PMID: 28900169 PMCID: PMC5595880 DOI: 10.1038/s41598-017-11647-6] [Citation(s) in RCA: 14] [Impact Index Per Article: 2.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 05/11/2017] [Accepted: 08/29/2017] [Indexed: 11/08/2022] Open
Abstract
The high field phenomena of inter-valley transfer and avalanching breakdown have long been exploited in devices based on conventional semiconductors. In this Article, we demonstrate the manifestation of these effects in atomically-thin WS2 field-effect transistors. The negative differential conductance exhibits all of the features familiar from discussions of this phenomenon in bulk semiconductors, including hysteresis in the transistor characteristics and increased noise that is indicative of travelling high-field domains. It is also found to be sensitive to thermal annealing, a result that we attribute to the influence of strain on the energy separation of the different valleys involved in hot-electron transfer. This idea is supported by the results of ensemble Monte Carlo simulations, which highlight the sensitivity of the negative differential conductance to the equilibrium populations of the different valleys. At high drain currents (>10 μA/μm) avalanching breakdown is also observed, and is attributed to trap-assisted inverse Auger scattering. This mechanism is not normally relevant in conventional semiconductors, but is possible in WS2 due to the narrow width of its energy bands. The various results presented here suggest that WS2 exhibits strong potential for use in hot-electron devices, including compact high-frequency sources and photonic detectors.
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Affiliation(s)
- G He
- 1Department of Electrical Engineering, University at Buffalo, the State University of New York, Buffalo, NY, 14260-1900, USA
| | - J Nathawat
- 1Department of Electrical Engineering, University at Buffalo, the State University of New York, Buffalo, NY, 14260-1900, USA
| | - C-P Kwan
- Department of Physics, University at Buffalo, the State University of New York, Buffalo, NY, 14260-1500, USA
| | - H Ramamoorthy
- 1Department of Electrical Engineering, University at Buffalo, the State University of New York, Buffalo, NY, 14260-1900, USA
| | - R Somphonsane
- Department of Physics, King Mongkut' s Institute of Technology Ladkrabang, Bangkok, 10520, Thailand
| | - M Zhao
- High-Frequency High-Voltage Device and Integrated Circuits Center, Institute of Microelectronics of Chinese Academy of Sciences, 3 Beitucheng West Road, Chaoyang District, Beijing, PR China
| | - K Ghosh
- 1Department of Electrical Engineering, University at Buffalo, the State University of New York, Buffalo, NY, 14260-1900, USA
| | - U Singisetti
- 1Department of Electrical Engineering, University at Buffalo, the State University of New York, Buffalo, NY, 14260-1900, USA
| | - N Perea-López
- Department of Physics and Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania, 16802, USA
| | - C Zhou
- Department of Materials Science and Engineering and Materials Research Institute, The Pennsylvania State University, University Park, Pennsylvania, 16802, USA
| | - A L Elías
- Department of Physics and Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania, 16802, USA
| | - M Terrones
- Department of Physics and Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania, 16802, USA
- Department of Materials Science and Engineering and Materials Research Institute, The Pennsylvania State University, University Park, Pennsylvania, 16802, USA
- Department of Chemistry and Materials Research Institute, The Pennsylvania State University, University Park, Pennsylvania, 16802, USA
| | - Y Gong
- Department of Materials Science and Nano Engineering, Rice University, Houston, TX, 77005, USA
| | - X Zhang
- Department of Materials Science and Nano Engineering, Rice University, Houston, TX, 77005, USA
| | - R Vajtai
- Department of Materials Science and Nano Engineering, Rice University, Houston, TX, 77005, USA
| | - P M Ajayan
- Department of Materials Science and Nano Engineering, Rice University, Houston, TX, 77005, USA
| | - D K Ferry
- School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, Arizona, 85287-5706, USA
| | - J P Bird
- 1Department of Electrical Engineering, University at Buffalo, the State University of New York, Buffalo, NY, 14260-1900, USA.
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17
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Wang F, Wang Z, Jiang C, Yin L, Cheng R, Zhan X, Xu K, Wang F, Zhang Y, He J. Progress on Electronic and Optoelectronic Devices of 2D Layered Semiconducting Materials. SMALL (WEINHEIM AN DER BERGSTRASSE, GERMANY) 2017; 13:1604298. [PMID: 28594452 DOI: 10.1002/smll.201604298] [Citation(s) in RCA: 33] [Impact Index Per Article: 4.7] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 12/29/2016] [Revised: 02/13/2017] [Indexed: 06/07/2023]
Abstract
2D layered semiconducting materials (2DLSMs) represent the thinnest semiconductors, holding many novel properties, such as the absence of surface dangling bonds, sizable band gaps, high flexibility, and ability of artificial assembly. With the prospect of bringing revolutionary opportunities for electronic and optoelectronic applications, 2DLSMs have prospered over the past twelve years. From materials preparation and property exploration to device applications, 2DLSMs have been extensively investigated and have achieved great progress. However, there are still great challenges for high-performance devices. In this review, we provide a brief overview on the recent breakthroughs in device optimization based on 2DLSMs, particularly focussing on three aspects: device configurations, basic properties of channel materials, and heterostructures. The effects from device configurations, i.e., electrical contacts, dielectric layers, channel length, and substrates, are discussed. After that, the affect of the basic properties of 2DLSMs on device performance is summarized, including crystal defects, crystal symmetry, doping, and thickness. Finally, we focus on heterostructures based on 2DLSMs. Through this review, we try to provide a guide to improve electronic and optoelectronic devices of 2DLSMs for achieving practical device applications in the future.
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Affiliation(s)
- Feng Wang
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
- University of Chinese Academy of Sciences, Beijing, 100049, China
| | - Zhenxing Wang
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
| | - Chao Jiang
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory for Standardization and Measurement for Nanotechnology, National Center for Nanoscience and Technology, Beijing, 100190, China
| | - Lei Yin
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
- University of Chinese Academy of Sciences, Beijing, 100049, China
| | - Ruiqing Cheng
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
- University of Chinese Academy of Sciences, Beijing, 100049, China
| | - Xueying Zhan
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
| | - Kai Xu
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
- University of Chinese Academy of Sciences, Beijing, 100049, China
| | - Fengmei Wang
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
- University of Chinese Academy of Sciences, Beijing, 100049, China
| | - Yu Zhang
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
| | - Jun He
- CAS Center for Excellence in Nanoscience, CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, National Center for Nanoscience and Technology, Beijing, 100190, China
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