Atomic Layer Deposition Process-Enabled Carrier Mobility Boosting in Field-Effect Transistors through a Nanoscale ZnO/IGO Heterojunction

Oxide and 2D TMD semiconductors for 3D DRAM cell transistors

As the downscaling of conventional dynamic random-access memory (DRAM) has reached its limits, 3D DRAM has been proposed as a next-generation DRAM cell architecture. However, incorporating silicon into 3D DRAM technology faces various challenges in securing cost-effective high cell transistor performance. Therefore, many researchers are exploring the application of next-generation semiconductor materials, such as transition oxide semiconductors (OSs) and metal dichalcogenides (TMDs), to address these challenges and to realize 3D DRAM. This study provides an overview of the proposed structures for 3D DRAM, compares the characteristics of OSs and TMDs, and discusses the feasibility of employing the OSs and TMDs as the channel material for 3D DRAM. Furthermore, we review recent progress in 3D DRAM using the OSs, discussing their potential to overcome challenges in silicon-based approaches.

Enhancing the Carrier Mobility and Bias Stability in Metal-Oxide Thin Film Transistors with Bilayer InSnO/a-InGaZnO Heterojunction Structure

In this study, the electrical performance and bias stability of InSnO/a-InGaZnO (ITO/a-IGZO) heterojunction thin-film transistors (TFTs) are investigated. Compared to a-IGZO TFTs, the mobility (µFE) and bias stability of ITO/a-IGZO heterojunction TFTs are enhanced. The band alignment of the ITO/a-IGZO heterojunction is analyzed by using X-ray photoelectron spectroscopy (XPS). A conduction band offset (∆EC) of 0.5 eV is observed in the ITO/a-IGZO heterojunction, resulting in electron accumulation in the formed potential well. Meanwhile, the ∆EC of the ITO/a-IGZO heterojunction can be modulated by nitrogen doping ITO (ITON), which can affect the carrier confinement and transport properties at the ITO/a-IGZO heterojunction interface. Moreover, the carrier concentration distribution at the ITO/a-IGZO heterointerface is extracted by means of TCAD silvaco 2018 simulation, which is beneficial for enhancing the electrical performance of ITO/a-IGZO heterojunction TFTs.

Highly Sensitive Broadband Polarized Photodetector Based on the As0.6P0.4/WSe2 Heterostructure toward Imaging and Optical Communication Application

Polarization-sensitive photodetectors based on two-dimensional anisotropic materials still encounter the issues of narrow spectral coverage and low polarization sensitivity. To address these obstacles, anisotropic As0.6P0.4 with a narrow band gap has been integrated with WSe2 to construct a type-II heterostructure, realizing a high-performance polarization-sensitive photodetector with broad spectral range from 405 to 2200 nm. By operating in photovoltaic mode at zero bias, the device shows a very low dark current of ∼0.02 picoampere, high responsivity of 492 m A/W, and high photoswitching ratio of 6 × 104, yielding a high specific detectivity of 1.4 × 1012 Jones. The strong in-plane anisotropy of As0.6P0.4 endows the device with a capability of polarization-sensitive detection with a high polarization ratio of 6.85 under a bias voltage. As an image sensor and signal receiver, the device shows great potential in imaging and optical communication applications. This work develops an anisotropic vdW heterojunction to realize polarization-sensitive photodetectors with wide spectral coverage, fast response, and high sensitivity, providing a new candidate for potential applications of polarization-resolved electronics and photonics.

Tailoring Subthreshold Swing in A-IGZO Thin-Film Transistors for Amoled Displays: Impact of Conversion Mechanism on Peald Deposition Sequences

Amorphous IGZO (a-IGZO) thin-film transistors (TFTs) are standard backplane electronics to power active-matrix organic light-emitting diode (AMOLED) televisions due to their high carrier mobility and negligible low leakage characteristics. Despite their advantages, limitations in color depth arise from a steep subthreshold swing (SS) (≤ 0.1 V/decade), necessitating costly external compensation for IGZO transistors. For mid-size mobile applications such as OLED tablets and notebooks, it is important to ensure controllable SS value (≥ 0.3 V/decade). In this study, a conversion mechanism during plasma-enhanced atomic layer deposition (PEALD) is proposed as a feasible route to control the SS. When a pulse of a diethylzinc (DEZn) precursor is exposed to the M2 O3 (M = In or Ga) surface layer, partial conversion of the underlying M2 O3 to ZnO is predicted on the basis of density function theory calculations. Notably, significant distinctions between In-Ga-Zn (Case I) and In-Zn-Ga (Case II) films are observed: Case II exhibits a lower growth rate and larger Ga/In ratio. Case II TFTs with a-IGZO (subcycle ratio of In:Ga:Zn = 3:1:1) show reasonable SS values (313 mV decade-1 ) and high mobility (µFE ) of 29.3 cm2 Vs-1 (Case I: 84 mV decade-1 and 33.4 cm2 Vs-1 ). The rationale for Case II's reasonable SS values is discussed, attributing it to the plausible formation of In-Zn defects, supported by technology computer-aided design (TCAD) simulations.

Progress, Challenges, and Opportunities in Oxide Semiconductor Devices: A Key Building Block for Applications Ranging from Display Backplanes to 3D Integrated Semiconductor Chips

As Si has faced physical limits on further scaling down, novel semiconducting materials such as 2D transition metal dichalcogenides and oxide semiconductors (OSs) have gained tremendous attention to continue the ever-demanding downscaling represented by Moore's law. Among them, OS is considered to be the most promising alternative material because it has intriguing features such as modest mobility, extremely low off-current, great uniformity, and low-temperature processibility with conventional complementary-metal-oxide-semiconductor-compatible methods. In practice, OS has successfully replaced hydrogenated amorphous Si in high-end liquid crystal display devices and has now become a standard backplane electronic for organic light-emitting diode displays despite the short time since their invention in 2004. For OS to be implemented in next-generation electronics such as back-end-of-line transistor applications in monolithic 3D integration beyond the display applications, however, there is still much room for further study, such as high mobility, immune short-channel effects, low electrical contact properties, etc. This study reviews the brief history of OS and recent progress in device applications from a material science and device physics point of view. Simultaneously, remaining challenges and opportunities in OS for use in next-generation electronics are discussed.

Piezotronic and Piezo-Phototronic Effects-Enhanced Core-Shell Structure-Based Nanowire Field-Effect Transistors

Piezotronic and piezo-phototronic effects have been extensively applied to modulate the performance of advanced electronics and optoelectronics. In this study, to systematically investigate the piezotronic and piezo-phototronic effects in field-effect transistors (FETs), a core-shell structure-based Si/ZnO nanowire heterojunction FET (HJFET) model was established using the finite element method. We performed a sweep analysis of several parameters of the model. The results show that the channel current increases with the channel radial thickness and channel doping concentration, while it decreases with the channel length, gate doping concentration, and gate voltage. Under a tensile strain of 0.39‱, the saturation current change rate can reach 38%. Finally, another core-shell structure-based ZnO/Si nanowire HJFET model with the same parameters was established. The simulation results show that at a compressive strain of -0.39‱, the saturation current change rate is about 18%, which is smaller than that of the Si/ZnO case. Piezoelectric potential and photogenerated electromotive force jointly regulate the carrier distribution in the channel, change the width of the channel depletion layer and the channel conductivity, and thus regulate the channel current. The research results provide a certain degree of reference for the subsequent experimental design of Zn-based HJFETs and are applicable to other kinds of FETs.

High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In_0.84Ga_0.16O or In_0.75Zn_0.25O), and a barrier layer (BL) (Ga₂O₃) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μ_FE) with band-like transport, steep gate swing (SS), and positive threshold voltage (V_TH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In_0.75Zn_0.25O/Ga₂O₃ NL TFT showed remarkable electrical performance: μ_FE of 77.1 ± 0.67 cm²/(V s), V_TH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and I_ON/OFF of 8.9 × 10⁹ with a low operation voltage range of ≤2 V and excellent stabilities (ΔV_TH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

High Mobility IZTO Thin-Film Transistors Based on Spinel Phase Formation at Low Temperature through a Catalytic Chemical Reaction

In this paper, In_0.22 Zn_δ Sn_{0.78- δ} O_{1.89- δ} (δ = 0.55) films with a single spinel phase are successfully grown at the low temperature of 300 °C through careful cation composition design and a catalytic chemical reaction. Thin-film transistors (TFTs) with amorphous In_{0 .22} Zn_δ Sn_{0.78- δ} O_{1.89- δ} (δ = 0.55) channel layers have a reasonable mobility of 41.0 cm² V^-1 s^-1 due to the synergic intercalation of In and Sn ions. In contrast, TFTs with polycrystalline spinel In_{0 .22} Zn_δ Sn_{0.78- δ} O_{1.89- δ} (δ = 0.55) channel layers, achieved through a metal-induced crystallization at 300 °C, exhibit a remarkably high field-effect mobility of ≈83.2 cm² V^-1 s^-1 and excellent stability against external gate bias stress, which is attributed to the uniform formation of the highly ordered spinel phase. The relationships between cation composition, microstructure, and performance for the In₂ O₃ -ZnO-SnO₂ ternary component system are investigated rigorously to attain in-depth understanding of the roles of various crystalline phases, including spinel Zn_{2- y} Sn_{1- y} In_{2 y} O₄ (y = 0.45), bixbyite In_{2-2 x} Zn_x In_x O₄ (x = 0.4), rutile SnO₂ , and a homologous compound of compound (ZnO)_k (In₂ O₃ ) (k = 5). This work concludes that the cubic spinel phase of Zn_{2- y} Sn_{1- y} In_{2 y} O₄ (y = 0.45) film is a strong contender as a substitute for semiconducting polysilicon as a backplane channel ingredient for mobile active-matrix organic light-emitting diode displays.

Hydrogen-Doping-Enabled Boosting of the Carrier Mobility and Stability in Amorphous IGZTO Transistors

This study investigated the effect of hydrogen (H) on the performance of amorphous In-Ga-Zn-Sn oxide (a-In_0.29Ga_0.35Zn_0.11Sn_0.25O) thin-film transistors (TFTs). Ample H in plasma-enhanced atomic layer deposition (PEALD)-derived SiO₂ can diffuse into the underlying a-IGZTO film during the postdeposition annealing (PDA) process, which affects the electrical properties of the resulting TFTs due to its donor behavior in the a-IGZTO. The a-In_0.29Ga_0.35Zn_0.11Sn_0.25O TFTs at the PDA temperature of 400 °C exhibited a remarkably higher field-effect mobility (μ_FE) of 85.9 cm²/Vs, a subthreshold gate swing (SS) of 0.33 V/decade, a threshold voltage (V_TH) of -0.49 V, and an I_ON/OFF ratio of ∼10⁸; these values are superior compared to those of unpassivated a-In_0.29Ga_0.35Zn_0.11Sn_0.25O TFTs (μ_FE = 23.3 cm²/Vs, SS = 0.36 V/decade, and V_TH = -3.33 V). In addition, the passivated a-In_0.29Ga_0.35Zn_0.11Sn_0.25O TFTs had good stability against the external gate bias duration. This performance change can be attributed to the substitutional H doping into oxygen sites (H_O) leading to a boost in n_e and μ_FE. In contrast, the beneficial H_O effect was barely observed for amorphous indium gallium zinc oxide (a-IGZO) TFTs, suggesting that the hydrogen-doping-enabled boosting of a-IGZTO TFTs is strongly related to the existence of Sn cations. Electronic calculations of V_O and H_O using density functional theory (DFT) were performed to explain this disparity. The introduction of SnO₂ in a-IGZO is predicted to cause a conversion from shallow V_O to deep V_O due to the lower formation energy of deep V_O, which is effectively created around Sn cations. The formation of H_O by H doping in the IGZTO facilitates the efficient connection of atomic states forming the conduction band more smoothly. This reduces the effective mass and enhances the carrier mobility.

High-Performance Thin-Film Transistor with Atomic Layer Deposition (ALD)-Derived Indium-Gallium Oxide Channel for Back-End-of-Line Compatible Transistor Applications: Cation Combinatorial Approach

In this paper, the feasibility of an indium-gallium oxide (In_2(1-x)Ga_2xO_y) film through combinatorial atomic layer deposition (ALD) as an alternative channel material for back-end-of-line (BEOL) compatible transistor applications is studied. The microstructure of random polycrystalline In₂O_y with a bixbyite structure was converted to the amorphous phase of In_2(1-x)Ga_2xO_y film under thermal annealing at 400 °C when the fraction of Ga is ≥29 at. %. In contrast, the enhancement in the orientation of the (222) face and subsequent grain size was observed for the In_1.60Ga_0.40O_y film with the intermediate Ga fraction of 20 at. %. The suitability as a channel layer was tested on the 10-nm-thick HfO₂ gate oxide where the natural length was designed to meet the requirement of short channel devices with a smaller gate length (<100 nm). The In_1.60Ga_0.40O_y thin-film transistors (TFTs) exhibited the high field-effect mobility (μ_FE) of 71.27 ± 0.98 cm²/(V s), low subthreshold gate swing (SS) of 74.4 mV/decade, threshold voltage (V_TH) of -0.3 V, and I_ON/OFF ratio of >10⁸, which would be applicable to the logic devices such as peripheral circuit of heterogeneous DRAM. The in-depth origin for this promising performance was discussed in detail, based on physical, optical, and chemical analysis.

Polycrystalline InGaO Thin-Film Transistors with Coplanar Structure Exhibiting Average Mobility of ≈78 cm2 V-1 s-1 and Excellent Stability for Replacing Current Poly-Si Thin-Film Transistors for Organic Light-Emitting Diode Displays

Highly ordered polycrystalline indium gallium oxide (PC-IGO) film is obtained by the crystallization of room temperature sputtered amorphous IGO on a hot plate at 350 °C for 1 h and then annealed for 1 h in an N₂ O environment. A high-density PC-IGO of ≈7.15 g cm^-3 with reduced oxygen vacancy (≈14.83%) and hydroxyl (OH) related defects (≈10.96%) has been obtained by N₂ O annealing. Self-aligned coplanar thin-film transistor (TFT) with the PC-IGO exhibits the average saturation mobility of 78.73 cm² V^-1 s^-1 , threshold voltage of -1.07 V, subthreshold swing of 0.147 V dec^-1 , and the on/off current ratio of over 10⁸ . The TFTs show excellent stability under bias-temperature stress with a negligible threshold voltage shift (ΔV_TH ) of + 0.1 and -0.1 V for the positive and negative bias stresses, respectively. The TFTs exhibit very stable environmental stability when the TFTs are stored under high humidity (85%) and a high temperature (85 °C) for 2 days. The ring oscillator and the gate driver mode of the PC-IGO TFTs exhibit the propagation delay of 7.44 ns/stage with rising/falling times of less than 0.7 μs, respectively. Therefore, the PC-IGO TFTs are suitable for large area, high-resolution active-matrix organic, and inorganic light-emitting diodes displays.

Enhanced Electrical Performance and Stability of Solution-Processed Thin-Film Transistors with In2O3/In2O3:Gd Heterojunction Channel Layer

The use of the semiconductor heterojunction channel layer has been explored as a method for improving the performance of metal oxide thin-film transistors (TFTs). The excellent electrical performance and stability of heterojunction TFTs is easy for vacuum-based techniques, but difficult for the solution process. Here, we fabricated In₂O₃/In₂O₃:Gd (In₂O₃/InGdO) heterojunction TFTs using a solution process and compared the electrical properties with single-layer In₂O₃ TFTs and In₂O₃:Gd (InGdO) TFTs. The In₂O₃/InGdO TFT consisted of a highly conductive In₂O₃ film as the primary transmission layer and a subconductive InGdO film as the buffer layer, and exhibited excellent electrical performance. Furthermore, by altering the Gd dopant concentration, we obtained an optimal In₂O₃/InGdO TFT with a higher saturation mobility (µ) of 4.34 cm²V^-1s^-1, a near-zero threshold voltage (V_th), a small off-state current (I_off) of 1.24×10-9 A, a large on/off current ratio (I_on/I_off) of 3.18×105, a small subthreshold swing (SS), and an appropriate positive bias stability (PBS). Finally, an aging test was performed after three months, indicating that In₂O₃/InGdO TFTs enable long-term air stability while retaining a high-mobility optimal switching property. This study suggests that the role of a high-performance In₂O₃/InGdO heterojunction channel layer fabricated by the solution process in the TFT is underlined, which further explores a broad pathway for the development of high-performance, low-cost, and large-area oxide electronics.

Comparative Study of Atomic Layer Deposited Indium-Based Oxide Transistors with a Fermi Energy Level-Engineered Heterojunction Structure Channel through a Cation Combinatorial Approach

Amorphous indium-gallium-zinc oxide (a-IGZO) has become a standard channel ingredient of switching/driving transistors in active-matrix organic light-emitting diode (AMOLED) televisions. However, mobile AMOLED displays with a high pixel density (≥500 pixels per inch) and good form factor do not often employ a-IGZO transistors due to their modest mobility (10-20 cm²/(V s)). Hybrid low-temperature polycrystalline silicon and oxide transistor (LTPO) technology is being adapted in high-end mobile AMOLED devices due to its ultralow power consumption and excellent current drivability. The critical issues of LTPO (including a complicated structure and high fabrication costs) require a search for alternative all-oxide thin-film transistors (TFTs) with low-cost processability and simple device architecture. The atomic layer deposition (ALD) method is a promising route for high-performance all-oxide TFTs due to its unique features, such as in situ cation composition tailoring ability, precise nanoscale thickness controllability, and excellent step coverage. Here, we report an in-depth comparative investigation of TFTs with indium-gallium oxide (IGO)/gallium-zinc oxide (GZO) and indium-zinc oxide (IZO)/GZO heterojunction stacks using an ALD method. IGO and IZO layers with different compositions were tested as a confinement layer (CL), whereas the GZO layer was used as a barrier layer (BL). Optimal IGO/GZO and IZO/GZO channels were carefully designed on the basis of their energy band properties, where the formation of a quasi-two-dimensional electron gas (q2DEG) near the CL/BL interface is realized by rational design of the band gaps and work-functions of the IGO, IZO, and GZO thin films. To verify the effect of q2DEG formation, the device performances and stabilities of TFTs with CL/BL oxide heterojunction stacks were examined and compared to those of TFTs with a single CL layer. The optimized device with the In_0.75Zn_0.25O/Ga_0.80Zn_0.20O stack showed remarkable electrical performance: μ_FE of 76.7 ± 0.51 cm²/(V s), V_TH of -0.37 ± 0.19 V, SS of 0.13 ± 0.01 V/dec, and I_ON/OFF of 2.5 × 10¹⁰ with low operation voltage range of ≥2 V and excellent stabilities (ΔV_TH of +0.35, -0.67, and +0.08 V for PBTS, NBIS, and CCS, respectively). This study suggests the feasibility of using high-performance ALD-derived oxide TFTs (which can compete with the performance of LTPO transistors) for high-end mobile AMOLED displays.

Analysis of Interface Phenomena for High-Performance Dual-Stacked Oxide Thin-Film Transistors via Equivalent Circuit Modeling

Oxide thin-film transistors (TFTs) have attracted much attention because they can be applied to flexible and large-scaled switching devices. Especially, oxide semiconductors (OSs) have been developed as active layers of TFTs. Among them, indium-gallium-zinc oxide (IGZO) is actively used in the organic light-emitting diode display field. However, despite their superior off-state properties, IGZO TFTs are limited by low field-effect mobility, which critically affects display resolution and power consumption. Herein, we determine new working mechanisms in dual-stacked OS, and based on this, we develop a dual-stacked OS-based TFT with improved performance: high field-effect mobility (∼80 cm²/V·s), ideal threshold voltage near 0 V, high on-off current ratio (>10⁹), and good stability at bias stress. Induced areas are formed at the interface by the band offset: band offset-induced area (BOIA) and BOIA-induced area (BIA). They connect the gate bias-induced area (GBIA) and electrode bias-induced area (EBIA), resulting in high current flow. Equivalent circuit modeling and the transmission line method are also introduced for more precise verification. By verifying current change with gate voltage in the single OS layer, the current flowing direction in the dual-stacked OS is calculated and estimated. This is powerful evidence to understand the conduction mechanism in a dual-stacked OS-based TFT, and it will provide new design rules for high-performance OS-based TFTs.

Achieving a Low-Voltage, High-Mobility IGZO Transistor through an ALD-Derived Bilayer Channel and a Hafnia-Based Gate Dielectric Stack

Ultrahigh-resolution displays for augmented reality (AR) and virtual reality (VR) applications require a novel architecture and process. Atomic-layer deposition (ALD) enables the facile fabrication of indium-gallium zinc oxide (IGZO) thin-film transistors (TFTs) on a substrate with a nonplanar surface due to its excellent step coverage and accurate thickness control. Here, we report all-ALD-derived TFTs using IGZO and HfO₂ as the channel layer and gate insulator, respectively. A bilayer IGZO channel structure consisting of a 10 nm base layer (In_0.52Ga_0.29Zn_0.19O) with good stability and a 3 nm boost layer (In_0.82Ga_0.08Zn_0.10O) with extremely high mobility was designed based on a cation combinatorial study of the ALD-derived IGZO system. Reducing the thickness of the HfO₂ dielectric film by the ALD process offers high areal capacitance in field-effect transistors, which allows low-voltage drivability and enhanced carrier transport. The intrinsic inferior stability of the HfO₂ gate insulator was effectively mitigated by the insertion of an ALD-derived 4 nm Al₂O₃ interfacial layer between HfO₂ and the IGZO film. The optimized bilayer IGZO TFTs with HfO₂-based gate insulators exhibited excellent performances with a high field-effect mobility of 74.0 ± 0.91 cm²/(V s), a low subthreshold swing of 0.13 ± 0.01 V/dec, a threshold voltage of 0.20 ± 0.24 V, and an I_ON/OFF of ∼3.2 × 10⁸ in a low-operation-voltage (≤2 V) range. This promising result was due to the synergic effects of a bilayer IGZO channel and HfO₂-based gate insulator with a high permittivity, which were mainly attributed to the effective carrier confinement in the boost layer with high mobility, low free carrier density of the base layer with a low V_O concentration, and HfO₂-induced high effective capacitance.