Charge Trapping in Amorphous Dielectrics for Secure Charge Storage

Smart pH Sensing: A Self-Sensitivity Programmable Platform with Multi-Functional Charge-Trap-Flash ISFET Technology

This study presents a novel pH sensor platform utilizing charge-trap-flash-type metal oxide semiconductor field-effect transistors (CTF-type MOSFETs) for enhanced sensitivity and self-amplification. Traditional ion-sensitive field-effect transistors (ISFETs) face challenges in commercialization due to low sensitivity at room temperature, known as the Nernst limit. To overcome this limitation, we explore resistive coupling effects and CTF-type MOSFETs, allowing for flexible adjustment of the amplification ratio. The platform adopts a unique approach, employing CTF-type MOSFETs as both transducers and resistors, ensuring efficient sensitivity control. An extended-gate (EG) structure is implemented to enhance cost-effectiveness and increase the overall lifespan of the sensor platform by preventing direct contact between analytes and the transducer. The proposed pH sensor platform demonstrates effective sensitivity control at various amplification ratios. Stability and reliability are validated by investigating non-ideal effects, including hysteresis and drift. The CTF-type MOSFETs' electrical characteristics, energy band diagrams, and programmable resistance modulation are thoroughly characterized. The results showcase remarkable stability, even under prolonged and repetitive operations, indicating the platform's potential for accurate pH detection in diverse environments. This study contributes a robust and stable alternative for detecting micro-potential analytes, with promising applications in health management and point-of-care settings.

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells-e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.