Comparative Study of Atomic Layer Deposited Indium-Based Oxide Transistors with a Fermi Energy Level-Engineered Heterojunction Structure Channel through a Cation Combinatorial Approach

Enhancing the Carrier Mobility and Bias Stability in Metal-Oxide Thin Film Transistors with Bilayer InSnO/a-InGaZnO Heterojunction Structure

In this study, the electrical performance and bias stability of InSnO/a-InGaZnO (ITO/a-IGZO) heterojunction thin-film transistors (TFTs) are investigated. Compared to a-IGZO TFTs, the mobility (µFE) and bias stability of ITO/a-IGZO heterojunction TFTs are enhanced. The band alignment of the ITO/a-IGZO heterojunction is analyzed by using X-ray photoelectron spectroscopy (XPS). A conduction band offset (∆EC) of 0.5 eV is observed in the ITO/a-IGZO heterojunction, resulting in electron accumulation in the formed potential well. Meanwhile, the ∆EC of the ITO/a-IGZO heterojunction can be modulated by nitrogen doping ITO (ITON), which can affect the carrier confinement and transport properties at the ITO/a-IGZO heterojunction interface. Moreover, the carrier concentration distribution at the ITO/a-IGZO heterointerface is extracted by means of TCAD silvaco 2018 simulation, which is beneficial for enhancing the electrical performance of ITO/a-IGZO heterojunction TFTs.

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V-1 s-1, subthreshold swing of 65 ± 1 mVdec-1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of - 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of - 2 MVcm-1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

c-Axis Aligned 3 nm Thick In2O3 Crystal Using New Liquid DBADMIn Precursor for Highly Scaled FET Beyond the Mobility-Stability Trade-off

Oxide semiconductors (OS) are attractive materials for memory and logic device applications owing to their low off-current, high field effect mobility, and superior large-area uniformity. Recently, successful research has reported the high field-effect mobility (μFE) of crystalline OS channel transistors (above 50 cm2 V-1 s-1). However, the memory and logic device application presents challenges in mobility and stability trade-offs. Here, we propose a method for achieving high-mobility and high-stability by lowering the grain boundary effect. A DBADMIn precursor was synthesized to deposit highly c-axis-aligned C(222) crystalline 3 nm thick In2O3 films. In this study, the 250 °C deposited 3 nm thick In2O3 channel transistor exhibited high μFE of 41.12 cm2 V-1 s-1, Vth of -0.50 V, and SS of 150 mV decade-1 with superior stability of 0.16 V positive shift during PBTS at 100 °C, 3 MV cm-1 stress conditions for 3 h.

Progress, Challenges, and Opportunities in Oxide Semiconductor Devices: A Key Building Block for Applications Ranging from Display Backplanes to 3D Integrated Semiconductor Chips

As Si has faced physical limits on further scaling down, novel semiconducting materials such as 2D transition metal dichalcogenides and oxide semiconductors (OSs) have gained tremendous attention to continue the ever-demanding downscaling represented by Moore's law. Among them, OS is considered to be the most promising alternative material because it has intriguing features such as modest mobility, extremely low off-current, great uniformity, and low-temperature processibility with conventional complementary-metal-oxide-semiconductor-compatible methods. In practice, OS has successfully replaced hydrogenated amorphous Si in high-end liquid crystal display devices and has now become a standard backplane electronic for organic light-emitting diode displays despite the short time since their invention in 2004. For OS to be implemented in next-generation electronics such as back-end-of-line transistor applications in monolithic 3D integration beyond the display applications, however, there is still much room for further study, such as high mobility, immune short-channel effects, low electrical contact properties, etc. This study reviews the brief history of OS and recent progress in device applications from a material science and device physics point of view. Simultaneously, remaining challenges and opportunities in OS for use in next-generation electronics are discussed.

High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In_0.84Ga_0.16O or In_0.75Zn_0.25O), and a barrier layer (BL) (Ga₂O₃) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μ_FE) with band-like transport, steep gate swing (SS), and positive threshold voltage (V_TH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In_0.75Zn_0.25O/Ga₂O₃ NL TFT showed remarkable electrical performance: μ_FE of 77.1 ± 0.67 cm²/(V s), V_TH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and I_ON/OFF of 8.9 × 10⁹ with a low operation voltage range of ≤2 V and excellent stabilities (ΔV_TH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In-Ga-Zn-O bilayer channel configuration

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In-Ga-Zn-O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 10⁹), low SS value (180 mV dec^-1), and high current drivability (13.6μAμm^-1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm^-1for 10⁴s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Hydrogen-Doping-Enabled Boosting of the Carrier Mobility and Stability in Amorphous IGZTO Transistors

This study investigated the effect of hydrogen (H) on the performance of amorphous In-Ga-Zn-Sn oxide (a-In_0.29Ga_0.35Zn_0.11Sn_0.25O) thin-film transistors (TFTs). Ample H in plasma-enhanced atomic layer deposition (PEALD)-derived SiO₂ can diffuse into the underlying a-IGZTO film during the postdeposition annealing (PDA) process, which affects the electrical properties of the resulting TFTs due to its donor behavior in the a-IGZTO. The a-In_0.29Ga_0.35Zn_0.11Sn_0.25O TFTs at the PDA temperature of 400 °C exhibited a remarkably higher field-effect mobility (μ_FE) of 85.9 cm²/Vs, a subthreshold gate swing (SS) of 0.33 V/decade, a threshold voltage (V_TH) of -0.49 V, and an I_ON/OFF ratio of ∼10⁸; these values are superior compared to those of unpassivated a-In_0.29Ga_0.35Zn_0.11Sn_0.25O TFTs (μ_FE = 23.3 cm²/Vs, SS = 0.36 V/decade, and V_TH = -3.33 V). In addition, the passivated a-In_0.29Ga_0.35Zn_0.11Sn_0.25O TFTs had good stability against the external gate bias duration. This performance change can be attributed to the substitutional H doping into oxygen sites (H_O) leading to a boost in n_e and μ_FE. In contrast, the beneficial H_O effect was barely observed for amorphous indium gallium zinc oxide (a-IGZO) TFTs, suggesting that the hydrogen-doping-enabled boosting of a-IGZTO TFTs is strongly related to the existence of Sn cations. Electronic calculations of V_O and H_O using density functional theory (DFT) were performed to explain this disparity. The introduction of SnO₂ in a-IGZO is predicted to cause a conversion from shallow V_O to deep V_O due to the lower formation energy of deep V_O, which is effectively created around Sn cations. The formation of H_O by H doping in the IGZTO facilitates the efficient connection of atomic states forming the conduction band more smoothly. This reduces the effective mass and enhances the carrier mobility.

High-Performance Thin-Film Transistor with Atomic Layer Deposition (ALD)-Derived Indium-Gallium Oxide Channel for Back-End-of-Line Compatible Transistor Applications: Cation Combinatorial Approach

In this paper, the feasibility of an indium-gallium oxide (In_2(1-x)Ga_2xO_y) film through combinatorial atomic layer deposition (ALD) as an alternative channel material for back-end-of-line (BEOL) compatible transistor applications is studied. The microstructure of random polycrystalline In₂O_y with a bixbyite structure was converted to the amorphous phase of In_2(1-x)Ga_2xO_y film under thermal annealing at 400 °C when the fraction of Ga is ≥29 at. %. In contrast, the enhancement in the orientation of the (222) face and subsequent grain size was observed for the In_1.60Ga_0.40O_y film with the intermediate Ga fraction of 20 at. %. The suitability as a channel layer was tested on the 10-nm-thick HfO₂ gate oxide where the natural length was designed to meet the requirement of short channel devices with a smaller gate length (<100 nm). The In_1.60Ga_0.40O_y thin-film transistors (TFTs) exhibited the high field-effect mobility (μ_FE) of 71.27 ± 0.98 cm²/(V s), low subthreshold gate swing (SS) of 74.4 mV/decade, threshold voltage (V_TH) of -0.3 V, and I_ON/OFF ratio of >10⁸, which would be applicable to the logic devices such as peripheral circuit of heterogeneous DRAM. The in-depth origin for this promising performance was discussed in detail, based on physical, optical, and chemical analysis.

Readily Accessible Metallic Micro-Island Arrays for High-Performance Metal Oxide Thin-Film Transistors

Thin-film transistors using metal oxide semiconductors are essential in many unconventional electronic devices. Nevertheless, further advances will be necessary to broaden their technological appeal. Here, a new strategy is reported to achieve high-performance solution-processed metal oxide thin-film transistors (MOTFTs) by introducing a metallic micro-island array (M-MIA) on top of the MO back channel, where the MO is a-IGZO (amorphous indium-gallium-zinc-oxide). Here Al-MIAs are fabricated using honeycomb cinnamate cellulose films, created by a scalable breath-figure method, as a shadow mask. For IGZO TFTs, the electron mobility (µ_e ) increases from ≈3.6 cm² V^-1 s^-1 to near 15.6 cm² V^-1 s^-1 for optimal Al-MIA dimension/coverage of 1.25 µm/51%. The Al-MIA IGZO TFT performance is superior to that of controls using compact/planar Al layers (Al-PL TFTs) and Au-MIAs with the same channel coverage. Kelvin probe force microscopy and technology computer-aided design simulations reveal that charge transfer occurs between the Al and the IGZO channel which is optimized for specific Al-MIA dimensions/surface channel coverages. Furthermore, such Al-MIA IGZO TFTs with a high-k fluoride-doped alumina dielectric exhibit a maximum µ_e of >50.2 cm² V^-1 s^-1 . This is the first demonstration of a micro-structured MO semiconductor heterojunction with submicrometer resolution metallic arrays for enhanced transistor performance and broad applicability to other devices.