Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays

Interface States in Gate Stack of Carbon Nanotube Array Transistors

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/μm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Inner Doping of Carbon Nanotubes with Perovskites for Ultralow Power Transistors

Semiconducting carbon nanotubes (CNTs) are considered as the most promising channel material to construct ultrascaled field-effect transistors, but the perfect sp2 C─C structure makes stable doping difficult, which limits the electrical designability of CNT devices. Here, an inner doping method is developed by filling CNTs with 1D halide perovskites to form a coaxial heterojunction, which enables a stable n-type field-effect transistor for constructing complementary metal-oxide-semiconductor electronics. Most importantly, a quasi-broken-gap (BG) heterojunction tunnel field-effect transistor (TFET) is first demonstrated based on an individual partial-filling CsPbBr3/CNT and exhibits a subthreshold swing of 35 mV dec-1 with a high on-state current of up to 4.9 µA per tube and an on/off current ratio of up to 105 at room temperature. The quasi-BG TFET based on the CsPbBr3/CNT coaxial heterojunction paves the way for constructing high-performance and ultralow power consumption integrated circuits.

Aligned carbon nanotube-based electronics on glass wafer

Carbon nanotubes (CNTs), due to excellent electronic properties, are emerging as a promising semiconductor for diverse electronic applications with superiority over silicon. However, until now, the supposed superiority of CNTs by "head-to-head" comparison within a well-defined voltage range remains unrealized. Here, we report aligned CNT (ACNT)-based electronics on a glass wafer and successfully develop a 250-nm gate length ACNT-based field-effect transistor (FET) with an almost identical transfer curve to a "90-nm" node silicon device, indicating a three- to four-generation superiority. Moreover, a record gate delay of 9.86 ps is achieved by our ring oscillator, which exceeds silicon even at a lower supply voltage. Furthermore, the fabrication of basic logic gates indicates the potential for further digital integrated circuits. All of these results highlight ACNT-based FETs on the glass wafer as an effective solution/platform for further development of CNT-based electronics.

Road map for, and technical challenges of, carbon-nanotube integrated circuit technology

A new targeted observational algorithm was developed to optimize prediction targets across various regions and variables. This approach was utilized to design an optimal ENSO monitoring array in the TPOS 2020 project.

Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors

Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current (IMIN) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of IMIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.