Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio

Spectrally Tunable Ultrafast Long Wave Infrared Detection at Room Temperature

Room-temperature longwave infrared (LWIR) detectors are preferred over cryogenically cooled solutions due to the cost effectiveness and ease of operation. The performance of present uncooled LWIR detectors such as microbolometers, is limited by reduced sensitivity, slow response time, and the lack of dynamic spectral tunability. Here, we present a graphene-based efficient room-temperature LWIR detector with high detectivity and fast response time utilizing its tunable optical and electronic characteristics. The inherent weak light absorption is enhanced by Dirac plasmons on the patterned graphene coupled to an optical cavity. The absorbed energy is converted into photovoltage by the Seebeck effect with an asymmetric carrier generation environment. Further, dynamic spectral tunability in the 8-12 μm LWIR band is achieved by electrostatic gating. The proposed detection platform paves the path to a fresh generation of uncooled graphene-based LWIR photodetectors for wide ranging applications such as molecular sensing, medical diagnostics, military, security and space.

Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction

We investigated the tunneling of graphene/insulator/metal heterojunctions by revising the Tsu-Esaki model of Fowler-Nordheim tunneling and direct tunneling current. Notably, the revised equations for both tunneling currents are proportional to V³, which originates from the linear dispersion of graphene. We developed a simulation tool by adopting revised tunneling equations using MATLAB. Thereafter, we optimized the device performance of the field-emission barristor by engineering the barrier height and thickness to improve the delay time, cut-off frequency, and power-delay product.

Hybrid Thin-Film Materials Combinations for Complementary Integration Circuit Implementation

Beyond conventional silicon, emerging semiconductor materials have been actively investigated for the development of integrated circuits (ICs). Considerable effort has been put into implementing complementary circuits using non-silicon emerging materials, such as organic semiconductors, carbon nanotubes, metal oxides, transition metal dichalcogenides, and perovskites. Whereas shortcomings of each candidate semiconductor limit the development of complementary ICs, an approach of hybrid materials is considered as a new solution to the complementary integration process. This article revisits recent advances in hybrid-material combination-based complementary circuits. This review summarizes the strong and weak points of the respective candidates, focusing on their complementary circuit integrations. We also discuss the opportunities and challenges presented by the prospect of hybrid integration.

Semiconductor-less vertical transistor with ION/IOFF of 106

Semiconductors have long been perceived as a prerequisite for solid-state transistors. Although switching principles for nanometer-scale devices have emerged based on the deployment of two-dimensional (2D) van der Waals heterostructures, tunneling and ballistic currents through short channels are difficult to control, and semiconducting channel materials remain indispensable for practical switching. In this study, we report a semiconductor-less solid-state electronic device that exhibits an industry-applicable switching of the ballistic current. This device modulates the field emission barrier height across the graphene-hexagonal boron nitride interface with I_ON/I_OFF of 10⁶ obtained from the transfer curves and adjustable intrinsic gain up to 4, and exhibits unprecedented current stability in temperature range of 15-400 K. The vertical device operation can be optimized with the capacitive coupling in the device geometry. The semiconductor-less switching resolves the long-standing issue of temperature-dependent device performance, thereby extending the potential of 2D van der Waals devices to applications in extreme environments.

Color-Selective Schottky Barrier Modulation for Optoelectric Logic

The limitation on signal processes implementable using conventional semiconductor circuits based on electric signals necessitates a revolutionary change in device structures such that they can exploit photons or light. Herein, we introduce optoelectric logic circuits that convert optical signals with different wavelengths corresponding to different colors into binary electric signals. Such circuits are assembled using unit devices in which the electric current through the semiconductor channel is effectively gated by lights of different colors. Color-selective optical modulation of the device is cleverly achieved using graphene decorated with different organic dyes as the electrode of a Schottky diode structure. The drastic change in the electrode work function under illumination induces a change in the height of the Schottky barrier formed at the electrode/semiconductor junction and consequent modulation of the electric current; we term the developed device a photonic barristor. We construct logic circuits using an array of photonic barristors and demonstrate that they execute the functions of conventional NAND and NOR gates from optical input signals.

Organic-based inverters: basic concepts, materials, novel architectures and applications

The review article covers the materials and techniques employed to fabricate organic-based inverter circuits and highlights their novel architectures, ground-breaking performances and potential applications.

All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics

In this study, we fabricated an array of all-inkjet-printed vertical Schottky barrier (SB) transistors and various logic gates on a large-area substrate. All of the electronic components, including the indium-gallium-zinc-oxide (IGZO) semiconductor, reduced graphene oxide (rGO), and indium-tin-oxide (ITO) electrodes, and the ion-gel gate dielectric, were directly and uniformly printed onto a 4 in. wafer. The vertical SB transistors had a vertically stacked structure, with the inkjet-printed IGZO semiconductor layer placed between the rGO source electrode and the ITO drain electrode. The ion-gel gate dielectric was also inkjet-printed in a coplanar gate geometry. The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density of 2.0 A·cm^-2, a high on-off current ratio of 10⁶, and excellent operational and environmental stabilities. The simple device structure of the vertical SB transistors was beneficial for the fabrication of all-inkjet-printed low-power logic circuits such as the NOT, NAND, and NOR gates on a large-area substrate.

Remote Gating of Schottky Barrier for Transistors and Their Vertical Integration

This paper introduces a strategy to modulate a Schottky barrier formed at a graphene-semiconductor heterojunction. The modulation is performed by controlling the work function of graphene from a gate that is placed laterally away from the graphene-semiconductor junction, which we refer to as the remote gating of a Schottky barrier. The remote gating relies on the sensitive work function of graphene, whose local variation induced by locally applied field effect affects the change in the work function of the entire material. Using Kelvin probe force microscopy analysis, we directly visualize how this local variation in the work function propagates through graphene. These properties of graphene are exploited to assemble remote-gated vertical Schottky barrier transistors (v-SBTs) in an unconventional device architecture. Furthermore, a vertical complementary circuit is fabricated by simply stacking two remote-gated v-SBTs (pentacene layer as the p-channel and indium gallium zinc oxide layer as the n-channel) vertically. We consider that the remote gating of graphene and the associated device architecture presented herein facilitate the extendibility of graphene-based v-SBTs in the vertical assembly of logic circuits.

Sub-2 V, Transfer-Stamped Organic/Inorganic Complementary Inverters Based on Electrolyte-Gated Transistors

Organic/inorganic hybrid complementary inverters operating at low voltages (1 V or less) were fabricated by transfer-stamping organic p-type poly(3-hexylthiophene) (P3HT) and inorganic n-type zinc oxide (ZnO) electrolyte-gated transistors (EGTs). A semicrystalline homopolymer-based gel electrolyte, or an ionogel, was also transfer-stamped on the semiconductors for use as a high-capacitance gate insulator. For the ionogel stamping, the thermoreversible crystallization of phase-separated homopolymer crystals, which act as network cross-links, was employed to improve the contact between the gel and the semiconductor channel. The homopolymer ionogel-gated P3HT transistor exhibited a high hole mobility of 2.81 cm²/(V s), and the ionogel-gated n-type ZnO transistors also showed a high electron mobility of 2.06 cm²/(V s). The transfer-stamped hybrid complementary inverter based on the P3HT and ZnO EGTs showed a low-voltage operation with appropriate inversion characteristics including a high voltage gain of ∼18. These results demonstrate that the transfer-stamping strategy provides a facile and reliable processing route for fabricating electrolyte-gated transistors and logic circuits.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

Synthesis, structure and applications of graphene-based 2D heterostructures

With the profuse amount of two-dimensional (2D) materials discovered and the improvements in their synthesis and handling, the field of 2D heterostructures has gained increased interest in recent years. Such heterostructures not only overcome the inherent limitations of each of the materials, but also allow the realization of novel properties by their proper combination. The physical and mechanical properties of graphene mean it has a prominent place in the area of 2D heterostructures. In this review, we will discuss the evolution and current state in the synthesis and applications of graphene-based 2D heterostructures. In addition to stacked and in-plane heterostructures with other 2D materials and their potential applications, we will also cover heterostructures realized with lower dimensionality materials, along with intercalation in few-layer graphene as a special case of a heterostructure. Finally, graphene heterostructures produced using liquid phase exfoliation techniques and their applications to energy storage will be reviewed.

Mobility Engineering in Vertical Field Effect Transistors Based on Van der Waals Heterostructures

Vertical integration of 2D layered materials to form van der Waals heterostructures (vdWHs) offers new functional electronic and optoelectronic devices. However, the mobility in vertical carrier transport in vdWHs of vertical field-effect transistor (VFET) is not yet investigated in spite of the importance of mobility for the successful application of VFETs in integrated circuits. Here, the mobility in VFET of vdWHs under different drain biases, gate biases, and metal work functions is first investigated and engineered. The traps in WSe₂ are the main source of scattering, which influences the vertical mobility and three distinct transport mechanisms: Ohmic transport, trap-limited transport, and space-charge-limited transport. The vertical mobility in VFET can be improved by suppressing the trap states by raising the Fermi level of WSe₂ . This is achieved by increasing the injected carrier density by applying a high drain voltage, or decreasing the Schottky barrier at the graphene/WSe₂ and metal/WSe₂ junctions by applying a gate bias and reducing the metal work function, respectively. Consequently, the mobility in Mn vdWH at +50 V gate voltage is about 76 times higher than the initial mobility of Au vdWH. This work enables further improvements in the VFET for successful application in integrated circuits.

A Hybrid Gate Dielectrics of Ion Gel with Ultra-Thin Passivation Layer for High-Performance Transistors Based on Two-Dimensional Semiconductor Channels

We propose a hybrid gate structure for ion gel dielectrics using an ultra-thin Al₂O₃ passivation layer for realizing high-performance devices based on electric-double-layer capacitors. Electric-double-layer transistors can be applied to practical devices with flexibility and transparency as well as research on the fundamental physical properties of channel materials; however, they suffer from inherent unwanted leakage currents between electrodes, especially for channel materials with low off-currents. Therefore, the Al₂O₃ passivation layer was introduced between the metal electrodes and ion gel film as a leakage current barrier; this simple approach effectively reduced the leakage current without capacitance degradation. In addition, we confirmed that a monolayer MoS₂ transistor fabricated with the proposed hybrid gate dielectric exhibited remarkably enhanced device properties compared to a transistor using a normal ion gel gate dielectric. Our findings on a simple method to improve the leakage current properties of ion gels could be applied extensively to realize high-performance electric-double-layer transistors utilizing various channel materials.

Ambipolar Barristors for Reconfigurable Logic Circuits

Vertical heterostructures based on graphene have emerged as a unique architecture for novel electronic devices with unusual characteristics. Here we report a new design of vertical ambipolar barristors based on metal-graphene-silicon-graphene sandwich structure, using the bottom graphene as a gate-tunable "active contact", the top graphene as an adaptable Ohmic contact, and the low doping thin silicon layer as the switchable channel. Importantly, with finite density of states and weak screening effect of graphene, we demonstrate, for the first time, that both the carrier concentration and majority carrier type in the sandwiched silicon can be readily modulated by gate potential penetrating through graphene. It can thus enable a new type of ambipolar barristors with an ON-OFF ratio exceeding 10³. Significantly, these ambipolar barristors can be flexibly configured into either p-type or n-type transistors and used to create integrated circuits with reconfigurable logic functions. This unconventional device structure and ambipolar reconfigurable characteristics can open up exciting opportunities in future electronics based on graphene or two-dimensional van der Waals heterostructures.

Gate-dependent asymmetric transport characteristics in pentacene barristors with graphene electrodes

We investigated the electrical characteristics and the charge transport mechanism of pentacene vertical hetero-structures with graphene electrodes. The devices are composed of vertical stacks of silicon, silicon dioxide, graphene, pentacene, and gold. These vertical heterojunctions exhibited distinct transport characteristics depending on the applied bias direction, which originates from different electrode contacts (graphene and gold contacts) to the pentacene layer. These asymmetric contacts cause a current rectification and current modulation induced by the gate field-dependent bias direction. We observed a change in the charge injection barrier during variable-temperature current-voltage characterization, and we also observed that two distinct charge transport channels (thermionic emission and Poole-Frenkel effect) worked in the junctions, which was dependent on the bias magnitude.

Extremely Large Gate Modulation in Vertical Graphene/WSe2 Heterojunction Barristor Based on a Novel Transport Mechanism

A WSe2 -based vertical graphene-transition metal dichalcogenide heterojunction barristor shows an unprecedented on-current increase with decreasing temperature and an extremely high on/off-current ratio of 5 × 10(7) at 180 K (3 × 10(4) at room temperature). These features originate from a trap-assisted tunneling process involving WSe2 defect states aligned near the graphene Dirac point.