Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution

Scalable Synaptic Transistor Memory from Solution-Processed Carbon Nanotubes for High-Speed Neuromorphic Data Processing

Neural networks as a core information processing technology in machine learning and artificial intelligence demand substantial computational resources to deal with the extensive multiply-accumulate operations. Neuromorphic computing is an emergent solution to address this problem, allowing the computation performed in memory arrays in parallel with high efficiencies conforming to the neural networks. Here, scalable synaptic transistor memories are developed from solution-sorted carbon nanotubes. The transistors exhibit a large switching ratio of over 105, a significant memory window of ≈12 V arising from charge trapping, and low response delays down to tens of nanoseconds. These device characteristics endow highly stabilized reconfigurable conductance states, successful emulation of synaptic functions, and a high data processing speed. Importantly, the devices exhibit uniform characteristic metrics, e.g., with a 1.8% variation in the memory window, suggesting an industrial-scale manufacturing capability of the fabrication. Using the memories, a hardware convolution kernel is designed and parallel image processing is demonstrated at a speed of 1 M bit per second per input channel. Given the efficacy of the convolution kernel, a promising prospect of the memories in implementing neuromorphic computing is envisaged. To explore the potential, large-scale convolution kernels are simulated and high-speed video processing is realized for autonomous driving.

Interface States in Gate Stack of Carbon Nanotube Array Transistors

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (Dit) to 6.1 × 1011 cm-2 eV-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (gm) of 2.42 mS/μm and an on-off ratio of 105. Further decreasing Dit below 1 × 1011 cm-2 eV-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.

Intense pH Sensitivity Modulation in Carbon Nanotube-Based Field-Effect Transistor by Non-Covalent Polyfluorene Functionalization

We compare the pH sensing performance of non-functionalized carbon nanotubes (CNT) field-effect transistors (p-CNTFET) and CNTFET functionalized with a conjugated polyfluorene polymer (labeled FF-UR) bearing urea-based moieties (f-CNTFET). The devices are electrolyte-gated, PMMA-passivated, 5 µm-channel FETs with unsorted, inkjet-printed single-walled CNT. In phosphate (PBS) and borate (BBS) buffer solutions, the p-CNTFETs exhibit a p-type operation while f-CNTFETs exhibit p-type behavior in BBS and ambipolarity in PBS. The sensitivity to pH is evaluated by measuring the drain current at a gate and drain voltage of -0.8 V. In PBS, p-CNTFETs show a linear, reversible pH response between pH 3 and pH 9 with a sensitivity of 26 ± 2.2%/pH unit; while f-CNTFETs have a much stronger, reversible pH response (373%/pH unit), but only over the range of pH 7 to pH 9. In BBS, both p-CNTFET and f-CNTFET show a linear pH response between pH 5 and 9, with sensitivities of 56%/pH and 96%/pH, respectively. Analysis of the I-V curves as a function of pH suggests that the increased pH sensitivity of f-CNTFET is consistent with interactions of FF-UR with phosphate ions in PBS and boric acid in BBS, with the ratio and charge of the complexed species depending on pH. The complexation affects the efficiency of electrolyte gating and the surface charge around the CNT, both of which modify the I-V response of the CNTFET, leading to the observed current sensitivity as a function of pH. The performances of p-CNTFET in PBS are comparable to the best results in the literature, while the performances of the f-CNTFET far exceed the current state-of-the-art by a factor of four in BBS and more than 10 over a limited range of pH in BBS. This is the first time that a functionalization other than carboxylate moieties has significantly improved the state-of-the-art of pH sensing with CNTFET or CNT chemistors. On the other hand, this study also highlights the challenge of transferring this performance to a real water matrix, where many different species may compete for interactions with FF-UR.

Improving the linearity of synaptic plasticity of single-walled carbon nanotube field-effect transistors via CdSe quantum dots decoration

The linearity of synaptic plasticity of single-walled carbon nanotube field-effect transistor (SWCNT FET) was improved by CdSe quantum dots decoration. The linearity of synaptic plasticity in SWCNT FET with decorating QDs was further improved by reducing the P-type doping level from the atmosphere. The synaptic behavior of SWCNT FET is found to be dominated by the charging and discharging processes of interface traps and surface traps, which are predominantly composed of H₂O/O₂redox couples. The improved synaptic behavior is mainly due to the reduction of the interface trap charging process after QDs decoration. The inherent correlation between the device synaptic behavior and the electron capture process of the traps are investigated through charging-based trap characterization. This study provides an effective scheme for improving linearity and designing new-type SWCNT synaptic devices.

Nanoscale Mapping of Carrier Mobilities in the Ballistic Transports of Carbon Nanotube Networks

Much progress has been made in the nanoscale analysis of nanostructures, while the mapping of key charge transport properties such as a carrier mobility remains a challenge, especially for one-dimensional systems. Here, we report the nanoscale mapping of carrier mobilities in carbon nanotube (CNT) networks and show that charge transport behaviors varied depending on network structures. In this work, the spatial distribution of localized charge transport properties such as mobilities and charge trap densities in CNT networks were mapped via a scanning noise microscopy. The mobility map was obtained from the conductivity maps measured at different back-gate biases, showing up to two orders of mobility variations depending on localized network structures. Furthermore, from the maps, correlations between mobility/conductivity and charge trap density were analyzed to determine charge transport mechanisms. In metallic CNT networks, the regions with rather high (low) or low (high) charge trap densities (mobilities) exhibited a diffusive or ballistic transport behavior, respectively. Interestingly, semiconducting CNT networks also exhibited a gradual transition from a diffusive to a ballistic transport behavior as the CNT mobility was increased by reaching the on-state with negative gate biases. The mapping of the cross-patterned CNT network showed that metallic CNT electrodes could achieve a good electrical contact with semiconducting CNTs without high contact resistance regions. Since this method allowed one to map versatile charge transport properties such as mobility, conductivity, and charge trap density, it can be a powerful tool for basic research about charge transport phenomena and practical device applications.

Analog-digital hybrid computing with SnS2 memtransistor for low-powered sensor fusion

Algorithms for intelligent drone flights based on sensor fusion are usually implemented using conventional digital computing platforms. However, alternative energy-efficient computing platforms are required for robust flight control in a variety of environments to reduce the burden on both the battery and computing power. In this study, we demonstrated an analog–digital hybrid computing platform based on SnS₂ memtransistors for low-power sensor fusion in drones. The analog Kalman filter circuit with memtransistors facilitates noise removal to accurately estimate the rotation of the drone by combining sensing data from the gyroscope and accelerometer. We experimentally verified that the power consumption of our hybrid computing-based Kalman filter is only 1/4^th of that of the traditional software-based Kalman filter.

Analog–digital hybrid computing based on SnS2 memtransistors is demonstrated for lowpower sensor fusion in drones, where a drone with hybrid computing performs sensor fusion with higher energy efficiency than that with only a digital processor.

Review-Hysteresis in Carbon Nano-Structure Field Effect Transistor

In recent decades, the research of nano-structure devices (e.g., carbon nanotube and graphene) has experienced rapid growth. These materials have supreme electronic, thermal, optical and mechanical properties and have received widespread concern in different fields. It is worth noting that gate hysteresis behavior of field effect transistors can always be found in ambient conditions, which may influence the transmission appearance. Many researchers have put forward various views on this question. Here, we summarize and discuss the mechanisms behind hysteresis, different influencing factors and improvement methods which help decrease or eliminate unevenness and asymmetry.

Boosting the electronic and catalytic properties of 2D semiconductors with supramolecular 2D hydrogen-bonded superlattices

The electronic properties of two-dimensional semiconductors can be strongly modulated by interfacing them with atomically precise self-assembled molecular lattices, yielding hybrid van der Waals heterostructures (vdWHs). While proof-of-concepts exploited molecular assemblies held together by lateral unspecific van der Waals interactions, the use of 2D supramolecular networks relying on specific non-covalent forces is still unexplored. Herein, prototypical hydrogen-bonded 2D networks of cyanuric acid (CA) and melamine (M) are self-assembled onto MoS₂ and WSe₂ forming hybrid organic/inorganic vdWHs. The charge carrier density of monolayer MoS₂ exhibits an exponential increase with the decreasing area occupied by the CA·M unit cell, in a cooperatively amplified process, reaching 2.7 × 10¹³ cm⁻² and thereby demonstrating strong n-doping. When the 2D CA·M network is used as buffer layer, a stark enhancement in the catalytic activity of monolayer MoS₂ for hydrogen evolution reactions is observed, outperforming the platinum (Pt) catalyst via gate modulation.

Here, the authors report the functionalization of monolayer transition metal dichalcogenides with hydrogen-bonded 2D supramolecular networks of cyanuric acid and melamine, leading to a pronounced n-doping effect and enhancement of MoS₂ catalytic activity for hydrogen evolution reactions.

Flexible Carbon Nanotube Synaptic Transistor for Neurological Electronic Skin Applications

There is an increasing interest in the development of memristive or artificial synaptic devices that emulate the neuronal activities for neuromorphic computing applications. While there have already been many reports on artificial synaptic transistors implemented on rigid substrates, the use of flexible devices could potentially enable an even broader range of applications. In this paper, we report artificial synaptic thin-film transistors built on an ultrathin flexible substrate using high carrier mobility semiconducting single-wall carbon nanotubes. The synaptic characteristics of the flexible synaptic transistor including long-term/short-term plasticity, spike-amplitude-dependent plasticity, spike-width-dependent plasticity, paired-pulse facilitation, and spike-time-dependent plasticity have all been systematically characterized. Furthermore, we have demonstrated a flexible neurological electronic skin and its peripheral nerve with a flexible ferroelectret nanogenerator (FENG) serving as the sensory mechanoreceptor that generates action potentials to be processed and transmitted by the artificial synapse. In such neurological electronic skin, the flexible FENG sensor converts the tactile input (magnitude and frequency of force) into presynaptic action potential pulses, which are then passed to the gate of the synaptic transistor to induce change in its postsynaptic current, mimicking the modulation of synaptic weight in a biological synapse. Our neurological electronic skin closely imitates the behavior of actual human skin, and it allows for instantaneous detection of force stimuli and offers biological synapse-like behavior to relay the stimulus signals to the next stage. The flexible sensory skin could potentially be used to interface with skeletal muscle fibers for applications in neuroprosthetic devices.

Rethinking the Characterization of Nanoscale Field-Effect Transistors: A Universal Approach

Standard methods for calculating transport parameters in nanoscale field-effect transistors (FETs), namely carrier concentration and mobility, require a linear connection between the gate voltage and channel conductance; however, this is often not the case. One reason often overlooked is that shifts in chemical and electric potential can partially compensate each other, commonly referred to as quantum capacitance. In nanoscale FETs, capacitance is often unmeasurable and an analytical formula is required, which assumes the conducting channel as metallic and common methods of determining threshold voltage no longer couple properly into transport equations. As present and future FET structures become smaller and have increased channel-gate coupling, this issue will render standard methods impossible to use. This work discusses the validity of common methods of characterization for nanoscale FETs, develops a universal model to determine transport properties by only measuring the threshold voltage of an FET and presents a new parameter to easily classify FETs as either quantum capacitance-limited or metallic approximated charge transport. Also considered in this work is electrical hysteresis from trap states and, in combination with the proposed universal model, novel techniques are introduced to measure and remove the errors associated with these effects often ignored in literature.

Solution-Processed Mixed-Dimensional Hybrid Perovskite/Carbon Nanotube Electronics

Benefiting from their extraordinary physical properties, methylammonium lead halide perovskites (PVKs) have attracted significant attention in optoelectronics. However, the PVK-based devices suffer from low carrier mobility and high operation voltage. Here, we utilize sorted semiconducting single-walled carbon nanotubes (95% s-SWCNTs) to enhance the performance of thin-film transistors (TFTs) based on the mixed-cation perovskite (MA_1-xFA_x)Pb(I_1-xBr_x)₃, enabling mixed-dimensional solution-processed electronics with high mobility (32.25 cm²/(V s)) and low voltage (∼3 V) operation. The resulting mixed-dimensional PVK/SWCNT TFTs possess ON/OFF ratios on the order of 10⁷, enabling the fabrication of high-gain inverters.

Ultrasensitive Stress Biomarker Detection Using Polypyrrole Nanotube Coupled to a Field-Effect Transistor

Stress biomarkers such as hormones and neurotransmitters in bodily fluids can indicate an individual’s physical and mental state, as well as influence their quality of life and health. Thus, sensitive and rapid detection of stress biomarkers (e.g., cortisol) is important for management of various diseases with harmful symptoms, including post-traumatic stress disorder and depression. Here, we describe rapid and sensitive cortisol detection based on a conducting polymer (CP) nanotube (NT) field-effect transistor (FET) platform. The synthesized polypyrrole (PPy) NT was functionalized with the cortisol antibody immunoglobulin G (IgG) for the sensitive and specific detection of cortisol hormone. The anti-cortisol IgG was covalently attached to a basal plane of PPy NT through an amide bond between the carboxyl group of PPy NT and the amino group of anti-cortisol IgG. The resulting field-effect transistor-type biosensor was utilized to evaluate various cortisol concentrations. Cortisol was sensitively measured to a detection limit of 2.7 × 10⁻¹⁰ M (100 pg/mL), with a dynamic range of 2.7 × 10⁻¹⁰ to 10⁻⁷ M; it exhibited rapid responses (<5 s). We believe that our approach can serve as an alternative to time-consuming and labor-intensive health questionnaires; it can also be used for diagnosis of underlying stress-related disorders.

Nanosystems, Edge Computing, and the Next Generation Computing Systems

It is widely recognized that nanoscience and nanotechnology and their subfields, such as nanophotonics, nanoelectronics, and nanomechanics, have had a tremendous impact on recent advances in sensing, imaging, and communication, with notable developments, including novel transistors and processor architectures. For example, in addition to being supremely fast, optical and photonic components and devices are capable of operating across multiple orders of magnitude length, power, and spectral scales, encompassing the range from macroscopic device sizes and kW energies to atomic domains and single-photon energies. The extreme versatility of the associated electromagnetic phenomena and applications, both classical and quantum, are therefore highly appealing to the rapidly evolving computing and communication realms, where innovations in both hardware and software are necessary to meet the growing speed and memory requirements. Development of all-optical components, photonic chips, interconnects, and processors will bring the speed of light, photon coherence properties, field confinement and enhancement, information-carrying capacity, and the broad spectrum of light into the high-performance computing, the internet of things, and industries related to cloud, fog, and recently edge computing. Conversely, owing to their extraordinary properties, 0D, 1D, and 2D materials are being explored as a physical basis for the next generation of logic components and processors. Carbon nanotubes, for example, have been recently used to create a new processor beyond proof of principle. These developments, in conjunction with neuromorphic and quantum computing, are envisioned to maintain the growth of computing power beyond the projected plateau for silicon technology. We survey the qualitative figures of merit of technologies of current interest for the next generation computing with an emphasis on edge computing.

Surfactant-driven Amphoteric Doping of Carbon Nanotubes

Aqueous surfactant dispersion is the most typical starting step to functionalize materials consisting of carbon nanotubes, but the effects of surfactants on the electronic properties are still unclear. Here we report how the functional groups of surfactants affect the electronic properties of carbon nanotube films. Using spectroscopic and thermoelectric characterization, we demonstrate that anionic and non-ionic surfactants contribute to the formation of p-type and n-type carbon nanotubes, respectively. Additionally, p-type doping with oxygen adsorption is found to compete with surfactants' doping. These findings are useful for designing the srarting carbon nanotube materials exhibiting desirable electronic properties.

Aligned Carbon Nanotube Synaptic Transistors for Large-Scale Neuromorphic Computing

This paper presents aligned carbon nanotube (CNT) synaptic transistors for large-scale neuromorphic computing systems. The synaptic behavior of these devices is achieved via charge-trapping effects, commonly observed in carbon-based nanoelectronics. In this work, charge trapping in the high- k dielectric layer of top-gated CNT field-effect transistors (FETs) enables the gradual analog programmability of the CNT channel conductance with a large dynamic range ( i. e., large on/off ratio). Aligned CNT synaptic devices present significant improvements over conventional memristor technologies ( e. g., RRAM), which suffer from abrupt transitions in the conductance modulation and/or a small dynamic range. Here, we demonstrate exceptional uniformity of aligned CNT FET synaptic behavior, as well as significant robustness and nonvolatility via pulsed experiments, establishing their suitability for neural network implementations. Additionally, this technology is based on a wafer-level technique for constructing highly aligned arrays of CNTs with high semiconducting purity and is fully CMOS compatible, ensuring the practicality of large-scale CNT+CMOS neuromorphic systems. We also demonstrate fine-tunability of the aligned CNT synaptic behavior and discuss its application to adaptive online learning schemes and to homeostatic regulation of artificial neuron firing rates. We simulate the implementation of unsupervised learning for pattern recognition using a spike-timing-dependent-plasticity scheme, indicate system-level performance (as indicated by the recognition accuracy), and demonstrate improvements in the learning rate resulting from tuning the synaptic characteristics of aligned CNT devices.

Performance enhancement of carbon nanotube thin film transistor by yttrium oxide capping

Carbon nanotube thin film transistors (CNT-TFTs) are regarded as promising technology for active matrix pixel driving circuits of future flat panel displays (FPD). For FPD application, unipolar thin film transistors (TFTs) with high mobility (μ), high on-state current (I_ON), low off-current (I_OFF) at high source/drain bias and small hysteresis are required simultaneously. Though excellent values of those performance metrics have been realized individually in different reports, the overall performance of previously reported CNT-TFTs has not met the above requirements. In this paper, we found that yttrium oxide (Y₂O₃) capping is helpful in improving both I_ON and μ of CNT-TFTs. Combining Y₂O₃ capping and Al₂O₃ passivation, unipolar CNT-TFTs with high I_ON/I_OFF (>10⁷) and low I_OFF (∼pA) at -10.1 V source/drain bias, and relatively small hysteresis in the range of -30 V to +30 V gate voltage were achieved, which are capable of active matrix display driving.

Investigating Limiting Factors in Stretchable All-Carbon Transistors for Reliable Stretchable Electronics

Stretchable form factors enable electronic devices to conform to irregular 3D structures, including soft and moving entities. Intrinsically stretchable devices have potential advantages of high surface coverage of active devices, improved durability, and reduced processing costs. This work describes intrinsically stretchable transistors composed of single-walled carbon nanotube (SWNT) electrodes and semiconductors and a dielectric that consists of a nonpolar elastomer. The use of a nonpolar elastomer dielectric enabled hysteresis-free device characteristics. Compared to devices on SiO₂ dielectrics, stretchable devices with nonpolar dielectrics showed lower mobility in ambient conditions because of the absence of doping from water. The effect of a SWNT band gap on device characteristics was investigated by using different SWNT sources as the semiconductor. Large-band-gap SWNTs exhibited trap-limited behavior caused by the low capacitance of the dielectric. In contrast, high-current devices based on SWNTs with smaller band gaps were more limited by contact resistance. Of the tested SWNT sources, SWNTs with a maximum diameter of 1.5 nm performed the best, with a mobility of 15.4 cm²/Vs and an on/off ratio >10³ for stretchable transistors. Large-band-gap devices showed increased sensitivity to strain because of a pronounced dependence on the dielectric thickness, whereas contact-limited devices showed substantially less strain dependence.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

Low Hysteresis Carbon Nanotube Transistors Constructed via a General Dry-Laminating Encapsulation Method on Diverse Surfaces

Electrical hysteresis in carbon nanotube thin-film transistor (CNTTFT) due to surface adsorption of H₂O/O₂ is a severe obstacle for practical applications. The conventional encapsulation methods based on vacuum-deposited inorganic materials or wet-coated organic materials have some limitations. In this work, we develop a general and highly efficient dry-laminating encapsulation method to reduce the hysteresis of CNTTFTs, which may simultaneously realize the construction and encapsulation of CNTTFT. Furthermore, by virtue of dry procedure and wide compatibility of PMMA, this method is suitable for the construction of CNTTFT on diverse surface including both inorganic and organic dielectric materials. Significantly, the dry-encapsulated CNTTFT exhibits very low or even negligible hysteresis with good repeatability and air stability, which is greatly superior to the nonencapsulated and wet-encapsulated CNTTFT with spin-coated PMMA. The dry-laminating encapsulation strategy, a kind of technological innovation, resolves a significant problem of CNTTFT and therefore will be promising in facile transferring and packaging the CNT films for high-performance optoelectronic devices.

Tuning the electrical performance and bias stability of a semiconducting SWCNT thin film transistor with an atomic layer deposited AlZrOx composite

Solution-processed semiconducting single-walled carbon nanotube (s-SWCNT) thin film transistors (TFTs) based on different atomic layer deposited AlZrO_x insulators are fabricated and characterized.

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics

Two-dimensional electronics based on single-layer (SL) MoS₂ offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS₂ circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS₂ FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.