Electrostatic dimension of aligned-array carbon nanotube field-effect transistors

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G 0 = 4e (2)/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G 0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm(-1), fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G 0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm(-1), which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm(-1) and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.

Recent Progress in Obtaining Semiconducting Single-Walled Carbon Nanotubes for Transistor Applications

High purity semiconducting single-walled carbon nanotubes (s-SWCNTs) with a narrow diameter distribution are required for high-performance transistors. Achieving this goal is extremely challenging because the as-grown material contains mixtures of s-SWCNTs and metallic- (m-) SWCNTs with wide diameter distributions, typically inadequate for integrated circuits. Since 2000, numerous ex situ methods have been proposed to improve the purity of the s-SWCNTs. The majority of these techniques fail to maintain the quality and integrity of the s-SWCNTs with a few notable exceptions. Here, the progress in realizing high purity s-SWCNTs in as-grown and post-processed materials is highlighted. A comparison of transistor parameters (such as on/off ratio and field-effect mobility) obtained from test structures establishes the effectiveness of various methods and suggests opportunities for future improvements.

Gate-Free Electrical Breakdown of Metallic Pathways in Single-Walled Carbon Nanotube Crossbar Networks

Aligned single-walled carbon nanotubes (SWNTs) synthesized by the chemical vapor deposition (CVD) method have exceptional potential for next-generation nanoelectronics. However, the coexistence of semiconducting (s-) and metallic (m-) SWNTs remains a considerable challenge since the latter causes significant degradation in device performance. Here we demonstrate a facile and effective approach to selectively break all m-SWNTs by stacking two layers of horizontally aligned SWNTs to form crossbars and applying a voltage to the crossed SWNT arrays. The introduction of SWNT junctions amplifies the disparity in resistance between s- and m-pathways, leading to a complete deactivation of m-SWNTs while minimizing the degradation of the semiconducting counterparts. Unlike previous approaches that required an electrostatic gate to achieve selectivity in electrical breakdown, this junction process is gate-free and opens the way for straightforward integration of thin-film s-SWNT devices. Comparison to electrical breakdown in junction-less SWNT devices without gating shows that this junction-based breakdown method yields more than twice the average on-state current retention in the resultant s-SWNT arrays. Systematic studies show that the on/off ratio can reach as high as 1.4 × 10(6) with a correspondingly high retention of on-state current compared to the initial current value before breakdown. Overall, this method provides important insight into transport at SWNT junctions and a simple route for obtaining pure s-SWNT thin film devices for broad applications.