Germanium-doped Metallic Ohmic Contacts in Black Phosphorus Field-Effect Transistors with Ultra-low Contact Resistance

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Silicon transistors are approaching their physical limit, calling for the emergence of a technological revolution. As the acknowledged ultimate version of transistor channels, 2D semiconductors are of interest for the development of post-Moore electronics due to their useful properties and all-in-one potentials. Here, the promise and current status of 2D semiconductors and transistors are reviewed, from materials and devices to integrated applications. First, we outline the evolution and challenges of silicon-based integrated circuits, followed by a detailed discussion on the properties and preparation strategies of 2D semiconductors and van der Waals heterostructures. Subsequently, the significant progress of 2D transistors, including device optimization, large-scale integration, and unconventional devices, are presented. We also examine 2D semiconductors for advanced heterogeneous and multifunctional integration beyond CMOS. Finally, the key technical challenges and potential strategies for 2D transistors and integrated circuits are also discussed. We envision that the field of 2D semiconductors and transistors could yield substantial progress in the upcoming years and hope this review will trigger the interest of scientists planning their next experiment.

Black Phosphorus Field-Effect Transistors with Improved Contact via Localized Joule Heating

Two-dimensional (2D) black phosphorus (BP) is considered an ideal building block for field-effect transistors (FETs) owing to its unique structure and intriguing properties. To achieve high-performance BP-FETs, it is essential to establish a reliable and low-resistance contact between the BP and the electrodes. In this study, we employed a localized Joule heating method to improve the contact between the 2D BP and gold electrodes, resulting in enhanced BP-FET performance. Upon applying a sufficiently large source-drain voltage, the zero-bias conductance of the device increased by approximately five orders of magnitude, and the linearity of the current-voltage curves was also enhanced. This contact improvement can be attributed to the formation of gold phosphide at the interface of the BP and the gold electrodes owing to current-generated localized Joule heat. The fabricated BP-FET demonstrated a high on/off ratio of 4850 and an on-state conductance per unit channel width of 1.25 μS μm-1, significantly surpassing those of the BP-FETs without electrical annealing. These findings offer a method to achieve a low-resistance BP/metal contact for developing high-performance BP-based electronic devices.

Black Phosphorus High-Frequency Transistors with Local Contact Bias

Having a sizable band gap and high carrier mobility, black phosphorus (BP) is a promising two-dimensional material for high-frequency electronic and optoelectronic devices. Further, for metal-oxide-semiconductor field-effect transistors (MOSFETs) operating at high frequencies, they must have a top gate of submicron length instead of the commonly used global back gate. However, without the global back gate to electrostatically induce doping in BP, top-gated submicron BP MOSFETs have not reached their full potential mainly due to large contact resistances. Here, we report top-gated submicron BP MOSFETs with local contact bias electrodes to induce doping in the contact region. This resulted in reduced contact resistance and, in turn, orders of magnitude improvement in current capacity (>500 μA/μm) and peak transconductance (>40 μS/μm), if compared with top-gated BP transistors without any back-gating scheme. In turn, these improvements resulted in a forward current gain cutoff frequency of 37 GHz and a maximum frequency of oscillation of 22 GHz at room temperature, the highest reported for BP MOSFETs up to date.

Black phosphorus electronics

As the scaling of silicon-based field-effect transistors has approached its physical limits, the search for alternative channel materials for future logic devices has attracted much attention. The discovery of graphene has unveiled another material family with layered structures called two-dimensional (2D) materials. Black phosphorus (BP), the most stable allotrope of phosphorus, was introduced as a new type of 2D material in 2014. Thanks to its high mobility, in-plane anisotropy and direct band gap, BP is considered to be a promising candidate for next-generation electronic and optoelectronic devices. Numerous studies have demonstrated the beneficial effects of introducing BP for device architectures. Herein, we present a review outlining recent progress towards high performance BP-based transistors. This review starts with the fundamental properties of BP, including its crystal structure, bandgap, and direct current (DC) and radio-frequency (RF) characteristics, followed by a detailed description of the modulation and application of those properties, involving anisotropy, functionalization and superlattices. Furthermore, we also discuss device design for high-performance transistors, with particular emphasis on interface engineering and device stability. Finally, we offer our perspective on the future of BP electronics, aiming to benefit colleagues who are interested in this exciting research field.

Negative Transconductance Heterojunction Organic Transistors and their Application to Full-Swing Ternary Circuits

Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H-TRs) exhibit negative transconductance (NTC) regions. Using the NTC characteristics of H-TRs, ternary inverters have recently been demonstrated. However, they have shown incomplete inverter characteristics; the output voltage (V_OUT ) does not fully swing from V_DD to G_ND . A new H-TR device structure that consists of a dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) layer stacked on a PTCDI-C13 layer is presented. Due to the continuous DNTT layer from source to drain, the proposed device exhibits novel switching behavior: p-type off/p-type subthreshold region /NTC/ p-type on. As a result, it has a very high on/off current ratio (≈10⁵ ) and exhibits NTC behavior. It is also demonstrated that an array of 36 of these H-TRs have 100% yield, a uniform on/off current ratio, and uniform NTC characteristics. Furthermore, the proposed ternary inverter exhibits full V_DD -to-G_ND swing of V_OUT with three distinct logic states. The proposed transistors and inverters exhibit hysteresis-free operation due to the use of a hydrophobic gate dielectric and encapsulating layers. Based on this, the transient operation of a ternary inverter circuit is demonstrated for the first time.