Ion Sputter Induced Interfacial Reaction in Prototypical Metal-GaN System

Formation Mechanism and Bandgap Reduction of GaN-ZnO Solid-Solution Thin Films Fabricated by Nanolamination of Atomic Layer Deposition

Nanolamination of GaN and ZnO layers by atomic layer deposition (ALD) is employed to fabricate GaN-ZnO homogenous solid-solution thin films because it offers more precise control of the stoichiometry. By varying the ALD cycle ratios of GaN:ZnO from 5:10 to 10:5, the (GaN)_{1- x} (ZnO)_x films with 0.39 ≦ x ≦ 0.79 are obtained. The formation of solid solution is explained based on the atomic stacking and preferred orientation of the layers of GaN and ZnO. However, the growth rates of GaN and ZnO during the lamination process are different from those of pure GaN and ZnO films. It is found that GaN grows faster on ZnO, whereas ZnO grows slower on GaN. The density functional theory (DFT) calculations are performed using a superlattice model for GaN and ZnO laminated layers fabricated by ALD to understand the difference of density of states (DOS) and evaluate the bandgaps for various atomic configurations in the solid-solution films. The band positions are experimentally defined by ultraviolet photoelectron spectroscopy. Significant bandgap reduction of the solid solutions is observed, which can be explained by the DOS from the DFT calculations. Visible-light-driven photocatalytic hydrogen evolution is conducted to confirm the applicability of the solid-solution films.

Formation and Applications in Electronic Devices of Lattice-Aligned Gallium Oxynitride Nanolayer on Gallium Nitride

Gallium nitride (GaN), a promising alternative semiconductor to Si, is widely used in photoelectronic and electronic technologies. However, the vulnerability of the GaN surface is a critical restriction that hinders the development of GaN-based devices, especially in terms of device stability and reliability. In this study, this challenge is overcome by converting the GaN surface into a gallium oxynitride (GaON) epitaxial nanolayer through an in situ two-step "oxidation-reconfiguration" process. The O plasma treatment overcomes the chemical inertness of the GaN surface, and sequential thermal annealing manipulates the kinetic-thermodynamic reaction pathways to create a metastable GaON nanolayer with a wurtzite lattice. The GaN-derived GaON nanolayer is a tailored structure for surface reinforcement and possesses several advantages, including a wide bandgap, high thermodynamic stability, and large valence band offset with a GaN substrate. These physical properties can be further leveraged to enhance the performance of GaN-based devices in various applications, such as power systems, complementary logic integrated circuits, photoelectrochemical water splitting, and ultraviolet photoelectric conversion.

Large-Sized Nanocrystalline Ultrathin β-Ga2O3 Membranes Fabricated by Surface Charge Lithography

Large-sized 2D semiconductor materials have gained significant attention for their fascinating properties in various applications. In this work, we demonstrate the fabrication of nanoperforated ultrathin β-Ga₂O₃ membranes of a nanoscale thickness. The technological route includes the fabrication of GaN membranes using the Surface Charge Lithography (SCL) approach and subsequent thermal treatment in air at 900 °C in order to obtain β-Ga₂O₃ membranes. The as-grown GaN membranes were discovered to be completely transformed into β-Ga₂O₃, with the morphology evolving from a smooth topography to a nanoperforated surface consisting of nanograin structures. The oxidation mechanism of the membrane was investigated under different annealing conditions followed by XPS, AFM, Raman and TEM analyses.

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (V_th) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al₂O₃) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V_th shift (ΔV_th) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.