The impact of dislocations on AlGaN/GaN Schottky diodes and on gate failure of high electron mobility transistors

Broadband Eddy Current Measurement of the Sheet Resistance of GaN Semiconductors

Although the classical four-point probe method usually provides adequate results, it is in many cases inappropriate for the measurement of thin sheet resistance, especially in the case of a buried conductive layer or if the surface contacts are oxidized/degraded. The surface concentration of dislocation defects in GaN samples is known to challenge this kind of measurement. For the GaN sample presented in this study, it even totally impaired the ability of this method to even provide results without a prior deposition of gold metallic contact pads. In this paper, we demonstrate the benefits of using a new broadband multifrequency noncontact eddy current method to accurately measure the sheet resistance of a complicated-to-measure epitaxy-grown GaN-doped sample. The benefits of the eddy current method compared to the traditional four-point method are demonstrated. The multilayer-doped GaN sample is perfectly evaluated, which will allow further development applications in this field. The point spread function of the probe used for this noncontact method was also evaluated using a 3D finite element model using CST-Studio Suite simulation software 2020 and experimental measurements.

Current-Limited Conductive Atomic Force Microscopy

Conductive atomic force microscopy (CAFM) has become the preferred tool of many companies and academics to analyze the electronic properties of materials and devices at the nanoscale. This technique scans the surface of a sample using an ultrasharp conductive nanoprobe so that the contact area between them is very small (<100 nm2) and it can measure the properties of the sample with a very high lateral resolution. However, measuring relatively low currents (∼1 nA) in such small areas produces high current densities (∼1000 A/cm2), which almost always results in fast nanoprobe degradation. That is not only expensive but also endangers the reliability of the data collected because detecting which data sets are affected by tip degradation can be complex. Here, we show an inexpensive long-sought solution for this problem by using a current limitation system. We test its performance by measuring the tunneling current across a reference ultrathin dielectric when applying ramped voltage stresses at hundreds of randomly selected locations of its surface, and we conclude that the use of a current limitation system increases the lifetime of the tips by a factor of ∼50. Our work contributes to significantly enhance the reliability of one of the most important characterization techniques in the field of nanoelectronics.

Scanning capacitance microscopy of GaN-based high electron mobility transistor structures: A practical guide

The scanning capacitance microscope (SCM) is a powerful tool to characterise local electrical properties in GaN-based high electron mobility transistor (HEMT) structures with nanoscale resolution. We investigated the experimental setup and the imaging conditions to optimise the SCM contrast. As to the experimental setup, we show that the desired tip should be sharp (e.g., with the tip radius of ≤25nm) and its coating should be made of conductive doped diamond. Most importantly, its spring constant should be large to achieve stable tip-sample contact. The selected tip should be positioned close to both the edge and Ohmic contact of the sample. Regarding the imaging conditions, we also show that a dc bias should be applied in addition to an ac bias because the latter alone is not sufficient to deplete the two-dimensional electron gas (2DEG) in the AlGaN/GaN heterostructure. The approximate range of the effective dc bias values was found by measuring the local dC/dV-V curves, yielding, after further optimisation, two optimised dc bias values which provide strong, but opposite, SCM contrast. In comparison, the selected ac bias value has no significant impact on the SCM contrast. The described methodology could potentially also be applied to other types of HEMT structures, and highly-doped samples.

Probing charge traps at the 2D semiconductor/dielectric interface

The family of 2-dimensional (2D) semiconductors is a subject of intensive scientific research due to their potential in next-generation electronics. While offering many unique properties like atomic thickness and chemically inert surfaces, the integration of 2D semiconductors with conventional dielectric materials is challenging. The charge traps at the semiconductor/dielectric interface are among many issues to be addressed before these materials can be of industrial relevance. Conventional electrical characterization methods remain inadequate to quantify the traps at the 2D semiconductor/dielectric interface since the estimations of the density of interface traps, Dit, by different techniques may yield more than an order-of-magnitude discrepancy, even when extracted from the same device. Therefore, the challenge to quantify Dit at the 2D semiconductor/dielectric interface is about finding an accurate and reliable measurement method. In this review, we discuss characterization techniques which have been used to study the 2D semiconductor/dielectric interface. Specifically, we discuss the methods based on small-signal AC measurements, subthreshold slope measurements and low-frequency noise measurements. While these approaches were developed for silicon-based technology, 2D semiconductor devices possess a set of unique challenges requiring a careful re-evaluation when using these characterization techniques. We examine the conventional methods based on their efficacy and accuracy in differentiating various types of trap states and provide guidance to find an appropriate method for charge trap analysis and estimation of Dit at 2D semiconductor/dielectric interfaces.

Comprehensive analysis of current leakage at individual screw and mixed threading dislocations in freestanding GaN substrates

The electrical characteristics of Schottky contacts on individual threading dislocations (TDs) with a screw-component in GaN substrates and the structures of these TDs were investigated to assess the effects of such defects on reverse leakage currents. Micrometer-scale platinum/GaN Schottky contacts were selectively fabricated on screw- and mixed-TD-related etch pits classified based on the pit size. Current-voltage (I-V) data acquired using conductive atomic force microscopy showed that very few of the screw TDs generated anomalously large reverse leakage currents. An analysis of the temperature dependence of the I-V characteristics established that the leakage current conduction mechanisms for the leaky screw TDs differed from those for the other screw and mixed TDs. Specifically, anomalous current leakage was generated by Poole-Frenkel emission and trap-assisted tunneling via distinctive trap states together with Fowler-Nordheim tunneling, with the mechanism changing according to variations in temperature and applied voltage. The leaky TDs were identified as Burgers vector b = 1c closed-core screw TDs having a helical morphology similar to that of other screw TDs generating small leakage currents. Based on the results, we proposed that the atomic-scale modification of the dislocation core structure related to interactions with point defects via dislocation climbing caused different leakage characteristics of the TDs.

Dislocation characterization inc-plane GaN epitaxial layers on 6 inch Si wafer with a fast second-harmonic generation intensity mapping technique

Second harmonic generation (SHG) intensity, Raman scattering stress, photoluminescence and reflected interference pattern are used to determine the distributions of threading dislocations (TDs) and horizontal dislocations (HDs) in thec-plane GaN epitaxial layers on 6 inch Si wafer which is a structure of high electron mobility transistor (HEMT). The Raman scattering spectra show that the TD and HD result in the tensile stress and compressive stress in the GaN epitaxial layers, respectively. Besides, the SHG intensity is confirmed that to be proportional to the stress value of GaN epitaxial layers, which explains the spatial distribution of SHG intensity for the first time. It is noted that the dislocation-mediated SHG intensity mapping image of the GaN epitaxial layers on 6 inch Si wafer can be obtained within 2 h, which can be used in the optimization of high-performance GaN based HEMTs.

Comprehensive Schottky Barrier Height Behavior and Reliability Instability with Ni/Au and Pt/Ti/Pt/Au on AlGaN/GaN High-Electron-Mobility Transistors

The reliability instability of inhomogeneous Schottky contact behaviors of Ni/Au and Pt/Ti/Pt/Au gate contacts on AlGaN/GaN high-electron-mobility transistors (HEMTs) was investigated via off-state stress and temperature. Under the off-state stress condition, Pt/Ti/Pt/Au HEMT showed abruptly reduced reverse leakage current, which improved the Schottky barrier height (SBH) from 0.46 to 0.69 eV by suppression of the interfacial donor state. As the temperature increased, the reverse leakage current of the Pt/Ti/Pt/Au AlGaN/GaN HEMT at 308 K showed more reduction under the same off-state stress condition while that of the Ni/Au AlGaN/GaN HEMT increased. However, with temperatures exceeding 308 K under the same off-state stress conditions, the reverse leakage current of the Pt/Ti/Pt/Au AlGaN/GaN HEMT increases, which can be intensified using the inverse piezoelectric effect. Based on this phenomenon, the present work reveals the necessity for analyzing the concurrent SBH and reliability instability due to the interfacial trap states of the MS contacts.