Experiment and simulation of single inhibitor SH110 for void-free TSV copper filling

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

Ultra-Uniform Copper Deposition in High Aspect Ratio Plated through Holes via Pulse-Reverse Plating

The uniformity and microstructure of the copper deposition in the high aspect ratio plated through holes (penetrating holes) are crucial for the performance of printed circuit board. We systematically investigated the effects of reverse pulse parameters in the period pulse reverse (PPR) plating on the uniformity and microstructure of the copper deposition, including reverse pulse frequency, reverse pulse duty cycle and reverse pulse current density. The Cu deposition behavior (throwing power) and its crystallographic characteristics, including grain size, crystallographic orientation, and grain boundary, were characterized by means of field-emission scanning electron microscopy (FE-SEM), X-ray diffractometer (XRD), and electron backscatter diffraction (EBSD). Our results clarify that the reverse pulse current density and duty ratio should be low to achieve the full filling and high uniformity of the through holes. The reverse pulse frequency of 1500 Hz would prevent the through holes to be fully filled. The copper electrodeposition in PTH prepared by double pulse electrodeposition has the good (111) surface texture and grain boundary distribution. This work demonstrated that the period pulse reverse (PPR) plating provides unique advantages in achieving the ultra-uniform copper deposition in the high aspect ratio plated through holes.

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.