Plasmonic CROWs for Tunable Dispersion and High Quality Cavity Modes

Accurate characterization of complex Bloch modes in optical chain waveguides using real-valued computations

This research presents a highly accurate and easy-to-implement method to characterize the complex Bloch modes propagating along optical chain waveguides with three-dimensional (3D) layered geometries and dispersive negative-epsilon material compositions. The technique combines commercial EM solver results with analytical post-processing to avoid iterative complex root estimation on the complex plane. The proposed methodology is based on the real-valued computations that yield the complex Bloch wavevector with superior accuracy even when both radiation and material losses are present. In addition, we introduce a single unit-cell technique to provide the possibility of dense meshing of 3D geometries when available computational resources are limited. To verify our results, two different plasmonic and dielectric case studies are discussed. The obtained results agree well with numerical and experimental results from the literature. Due to its generality, robustness, and high accuracy, the method is beneficial for studying a large variety of waveguide-based nanophotonic components.

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.