Water-Soluble Reactive Polymer Blends for Stable Memory Layers in Low-Voltage Nonvolatile Organic Memory Transistors with High Mobility and Data-Retention Characteristics

Here we demonstrate low-voltage nonvolatile organic memory transistors, featuring high charge-carrier mobility and outstanding data-retention characteristics, by employing water-soluble reactive polymer blends as a gate-insulating memory layer. Blend films of poly(vinyl alcohol) (PVA) and poly(2-acrylamido-2-methyl-1-propanesulfonic acid) (PAMPSA) (PVA:PAMPSA) were prepared from their aqueous solutions with various molar ratios of PAMPSA (0∼18 mol%) and thermally annealed at 70 ℃ and 110 ℃. Organic field-effect transistors (OFETs) were fabricated by depositing poly(3-hexylthiophene) (P3HT) channel layers on the thermally-treated PVA:PAMPSA films. Results showed that the hole mobility of OFETs was remarkably increased (ca. 294 times at 70 ℃ and ca. 42 times at 110 ℃) by adding only 2 mol% PAMPSA to the PVA films and further improved at 10 mol% PAMPSA (>11.7 cm2/Vs at 70 ℃ and >3.8 cm2/Vs at 110 ℃). The hysteresis characteristics were rather strengthened for the PVA:PAMPSA layers by annealing at 110 ℃ due to the formation of cross-linking sites, even though the OFETs with the pristine PVA layers did almost lose hysteresis characteristics at 110 ℃. The optimized OFETs with the PVA:PAMPSA layers (10 mol%, 110 ℃) delivered excellent data retention characteristics during >10,000 memory cycles at a voltage range of -5 ∼ +5 V. This article is protected by copyright. All rights reserved.

High-Performance Non-Volatile InGaZnO Based Flash Memory Device Embedded with a Monolayer Au Nanoparticles

Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from -20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 104 s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology.

Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-Au(NPs)) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-Au(NP))(n) films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO2 gate dielectric layer. For a single AuNP layer (i.e. PAD/TOA-Au(NP))1) with a number density of 1.82 × 10(12) cm(-2), the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four Au(NP) layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔV(th)) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 10(6)) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate.

Solution processed molecular floating gate for flexible flash memories

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

A low voltage programmable unipolar inverter with a gold nanoparticle monolayer on plastic

A programmable low voltage unipolar inverter with saturated-load configuration has been demonstrated on a plastic substrate. A self-assembled monolayer of gold (Au) nanoparticles was inserted into the dielectric layer acting as a charge trapping layer. The inverter operated well with supply voltages of < - 5 V and the switching voltage was tuned in a wide range under low program/erase bias. The retention and endurance test at ambient conditions confirmed the reliability of the inverter. Furthermore, the programmable behavior was maintained well at various bending states, demonstrating the adequate flexibility of our devices.