High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage

Probing the photovoltaic properties of Ga-doped CdS–Cu2S core–shell heterostructured nanowire devices

In this study Ga-doped cadmium sulfide (CdS) nanowires (NWs) were grown through chemical vapor deposition.

Label-free SnO2 nanowire FET biosensor for protein detection

Novel tin oxide field-effect-transistors (SnO₂ NW-FET) for pH and protein detection applicable in the healthcare sector are reported. With a SnO₂ NW-FET the proof-of-concept of a bio-sensing device is demonstrated using the carrier transport control of the FET channel by a (bio-) liquid modulated gate. Ultra-thin Al₂O₃ fabricated by a low temperature atomic layer deposition (ALD) process represents a sensitive layer to H⁺ ions safeguarding the nanowire at the same time. Successful pH sensitivity is demonstrated for pH ranging from 3 to 10. For protein detection, the SnO₂ NW-FET is functionalized with a receptor molecule which specifically interacts with the protein of interest to be detected. The feasibility of this approach is demonstrated via the detection of a biotinylated protein using a NW-FET functionalized with streptavidin. An immediate label-free electronic read-out of the signal is shown. The well-established Enzyme-Linked Immunosorbent Assay (ELISA) method is used to determine the optimal experimental procedure which would enable molecular binding events to occur while being compatible with a final label-free electronic read-out on a NW-FET. Integration of the bottom-up fabricated SnO₂ NW-FET pH- and biosensor into a microfluidic system (lab-on-a-chip) allows the automated analysis of small volumes in the 400 μl range as would be desired in portable on-site point-of-care (POC) devices for medical diagnosis.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Low-Programmable-Voltage Nonvolatile Memory Devices Based on Omega-shaped Gate Organic Ferroelectric P(VDF-TrFE) Field Effect Transistors Using p-type Silicon Nanowire Channels

A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)). We overcame the interfacial layer problem by incorporating P(VDF-TrFE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 10⁵, a long retention time greater than 3 × 10⁴ s, and a high endurance of over 10⁵ programming cycles while maintaining an I _ON/I _OFF ratio higher than 10².