Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors

In2O3 Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

Heat dissipation is a key issue for scaling metal-oxide-semiconductor field-effect transistors (MOSFETs). The Boltzmann distribution of electrons imposes a physical limit on the subthreshold swing (SS), which impedes both the reduction of the switching energy and the further increase of the device density. The negative capacitance effect is proposed to rescue MOSFETs from this phenomenon called "Boltzmann tyranny". Herein, we report In₂O₃ nanowire (NW) transistors with SS values in the sub-60 mV/dec region, which utilize the ferroelectric P(VDF-TrFE) as the dielectric layer. An ultralow SS down to ∼10 mV/dec is observed and spans over 5 orders of magnitude in the drain current. Meanwhile, a high on/off ratio of more than 10⁸ and a transconductance ( g_m) of 2.3 μS are obtained simultaneously at V_d = 0.1 V. The results can be understood by the "voltage amplification" effect induced from the negative capacitance effect. Moreover, the steep slope FET-based inverters indicate a high voltage gain of 41.6. In addition to the NOR and NAND gates, the Schmitt trigger inverters containing only one steep slope FET are demonstrated. This work demonstrates an avenue for low-power circuit design with a steep SS.

Organic ferroelectric/semiconducting nanowire hybrid layer for memory storage

Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and semiconducting nanowires over an insulating substrate, the ferroelectric dipole moment can be stabilized by injected free charge carriers accumulating laterally in the neighboring semiconducting nanowires. This lateral electrostatic coupling between ferroelectric and semiconducting nanowires offers new opportunities to design new device architectures. As an example, we demonstrate the fabrication of an elementary non-volatile memory device in a transistor-like configuration, of which the source-drain current exhibits a typical hysteretic behavior with respect to the poling voltage. The potential for size reduction intrinsic to the nanostructured hybrid layer offers opportunities for the development of strongly miniaturized ferroelectric and piezoelectric devices.