Recent advances in Sb-based III-V nanowires

Diameter Control of GaSb Nanowires Revealed by In Situ Environmental Transmission Electron Microscopy

Several nanowire properties are strongly dependent on their diameter, which is notoriously difficult to control for III-Sb nanowires compared with other III-V nanowires. Herein environmental transmission electron microscopy is utilized to study the growth of Au nanoparticle seeded GaSb nanowires in situ. In this study, the real time changes to morphology and nanoparticle composition as a result of precursor V/III ratio are investigated. For a wide range of the growth parameters, it is observed that decreasing the V/III ratio increases the nanoparticle volume through Ga accumulation in the nanoparticle. The increase in nanoparticle volume in turn forces the nanowire diameter to expand. The effect of the V/III ratio on diameter allows the engineering of diameter modulated nanowires, where the modulation persisted after the growth. Lastly, this study demonstrates the observed trends can be reproduced in a conventional ex situ system, highlighting the transferability and importance of the results obtained in situ.

Self-Catalyzed InSb/InAs Quantum Dot Nanowires

The nanowire platform offers great opportunities for improving the quality and range of applications of semiconductor quantum wells and dots. Here, we present the self-catalyzed growth of InAs/InSb/InAs axial heterostructured nanowires with a single defect-free InSb quantum dot, on Si substrates, by chemical beam epitaxy. A systematic variation of the growth parameters for the InAs top segment has been investigated and the resulting nanowire morphology analyzed. We found that the growth temperature strongly influences the axial and radial growth rates of the top InAs segment. As a consequence, we can reduce the InAs shell thickness around the InSb quantum dot by increasing the InAs growth temperature. Moreover, we observed that both axial and radial growth rates are enhanced by the As line pressure as long as the In droplet on the top of the nanowire is preserved. Finally, the time evolution of the diameter along the entire length of the nanowires allowed us to understand that there are two In diffusion paths contributing to the radial InAs growth and that the interplay of these two mechanisms together with the total length of the nanowires determine the final shape of the nanowires. This study provides insights in understanding the growth mechanisms of self-catalyzed InSb/InAs quantum dot nanowires, and our results can be extended also to the growth of other self-catalyzed heterostructured nanowires, providing useful guidelines for the realization of quantum structures with the desired morphology and properties.

Recent Progress on the Gold-Free Integration of Ternary III-As Antimonide Nanowires Directly on Silicon

During the last few years, there has been renewed interest in the monolithic integration of gold-free, Ternary III–As Antimonide (III–As–Sb) compound semiconductor materials on complementary metal-oxide-semiconductor (CMOS)—compatible silicon substrate to exploit its scalability, and relative abundance in high-performance and cost-effective integrated circuits based on the well-established technology. Ternary III–As–Sb nanowires (NWs) hold enormous promise for the fabrication of high-performance optoelectronic nanodevices with tunable bandgap. However, the direct epitaxial growth of gold-free ternary III–As–Sb NWs on silicon is extremely challenging, due to the surfactant effect of Sb. This review highlights the recent progress towards the monolithic integration of III–As–Sb NWs on Si. First, a comprehensive and in-depth review of recent progress made in the gold-free growth of III–As–Sb NWs directly on Si is explicated, followed by a detailed description of the root cause of Sb surfactant effect and its influence on the morphology and structural properties of Au-free ternary III–As–Sb NWs. Then, the various strategies that have been successfully deployed for mitigating the Sb surfactant effect for enhanced Sb incorporation are highlighted. Finally, recent advances made in the development of CMOS compatible, Ternary III–As–Sb NWs based, high-performance optoelectronic devices are elucidated.