Understanding ambipolar transport in MoS2 field effect transistors: the substrate is the key

Reliable wafer-scale integration of two-dimensional materials and metal electrodes with van der Waals contacts

Since the first report on single-layer MoS2 based transistor, rapid progress has been achieved in two-dimensional (2D) material-based atomically thin electronics, providing an alternative approach to solve the bottleneck in silicon device miniaturization. In this scenario, reliable contact between the metal electrodes and the subnanometer-thick 2D materials becomes crucial in determining the device performance. Here, utilizing the quasi-van der Waals (vdW) epitaxy of metals on fluorophlogopite mica, we demonstrate an all-stacking method for the fabrication of 2D devices with high-quality vdW contacts by mechanically transferring pre-deposited metal electrodes. This technique is applicable for complex device integration with sizes up to the wafer scale and is also capable of tuning the electric characteristics of the interfacial junctions by transferring selective metals. Our results provide an efficient, scalable, and low-cost technique for 2D electronics, allowing high-density device integration as well as a handy tool for fundamental research in vdW materials.

Self-Expansion Based Multi-Patterning for 2D Materials Fabrication beyond the Lithographical Limit

Two-dimensional (2D) materials are promising successors for silicon transistor channels in ultimately scaled devices, necessitating significant research efforts to study their behavior at nanoscopic length scales. Unfortunately, current research has limited itself to direct patterning approaches, which limit the achievable resolution to the diffraction limit and introduce unwanted defects into the 2D material. The potential of multi-patterning to fabricate 2D materials features with unprecedented precision and low complexity at large scale is demonstrated here. By combining lithographic patterning of a mandrel and bottom-up self-expansion, this approach enables pattern resolution one order of magnitude below the lithographical resolution. In-depth characterization of the self-expansion double patterning (SEDP) process reveals the ability to manipulate the critical dimension with nanometer precision through a self-limiting and temperature-controlled oxidation process. These results indicate that the SEDP process can regain the quality and morphology of the 2D material, as shown by high-resolution microscopy and optical spectroscopy. This approach is shown to open up new avenues for research into high-performance, ultra-scaled 2D materials devices for future electronics.

Direct Assessment of Defective Regions in Monolayer MoS2 Field-Effect Transistors through In Situ Scanning Probe Microscopy Measurements

Implementing two-dimensional materials in field-effect transistors (FETs) offers the opportunity to continue the scaling trend in the complementary metal-oxide-semiconductor technology roadmap. Presently, the search for electrically active defects, in terms of both their density of energy states and their spatial distribution, has turned out to be of paramount importance in synthetic transition metal dichalcogenides layers, as they are suspected of severely inhibiting these devices from achieving their highest performance. Although advanced microscopy tools have allowed the direct detection of physical defects such as grain boundaries and point defects, their implementation at the device scale to assess the active defect distribution and their impact on field-induced channel charge modulation and current transport is strictly restrained. Therefore, it becomes critical to directly probe the gate modulation effect on the carrier population at the nanoscale of an FET channel, with the objective to establish a direct correlation with the device characteristics. Here, we have investigated the active channel in a monolayer MoS2 FET through in situ scanning probe microscopy, namely, Kelvin probe force microscopy and scanning capacitance microscopy, to directly identify active defect sites and to improve our understanding of the contribution of grain boundaries, bilayer islands, and defective grain domains to channel conductance.

Mechanism of Fermi Level Pinning for Metal Contacts on Molybdenum Dichalcogenide

The high contact resistance of transition metal dichalcogenide (TMD)-based devices is receiving considerable attention due to its limitation on electronic performance. The mechanism of Fermi level (EF) pinning, which causes the high contact resistance, is not thoroughly understood to date. In this study, the metal (Ni and Ag)/Mo-TMD surfaces and interfaces are characterized by X-ray photoelectron spectroscopy, atomic force microscopy, scanning tunneling microscopy and spectroscopy, and density functional theory systematically. Ni and Ag form covalent and van der Waals (vdW) interfaces on Mo-TMDs, respectively. Imperfections are detected on Mo-TMDs, which lead to electronic and spatial variations. Gap states appear after the adsorption of single and two metal atoms on Mo-TMDs. The combination of the interface reaction type (covalent or vdW), the imperfection variability of the TMD materials, and the gap states induced by contact metals with different weights are concluded to be the origins of EF pinning.

Light sources with bias tunable spectrum based on van der Waals interface transistors

Light-emitting electronic devices are ubiquitous in key areas of current technology, such as data communications, solid-state lighting, displays, and optical interconnects. Controlling the spectrum of the emitted light electrically, by simply acting on the device bias conditions, is an important goal with potential technological repercussions. However, identifying a material platform enabling broad electrical tuning of the spectrum of electroluminescent devices remains challenging. Here, we propose light-emitting field-effect transistors based on van der Waals interfaces of atomically thin semiconductors as a promising class of devices to achieve this goal. We demonstrate that large spectral changes in room-temperature electroluminescence can be controlled both at the device assembly stage -by suitably selecting the material forming the interfaces- and on-chip, by changing the bias to modify the device operation point. Even though the precise relation between device bias and kinetics of the radiative transitions remains to be understood, our experiments show that the physical mechanism responsible for light emission is robust, making these devices compatible with simple large areas device production methods.

Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning

Electronic devices based on two-dimensional semiconductors suffer from limited electrical stability because charge carriers originating from the semiconductors interact with defects in the surrounding insulators. In field-effect transistors, the resulting trapped charges can lead to large hysteresis and device drifts, particularly when common amorphous gate oxides (such as silicon or hafnium dioxide) are used, hindering stable circuit operation. Here, we show that device stability in graphene-based field-effect transistors with amorphous gate oxides can be improved by Fermi-level tuning. We deliberately tune the Fermi level of the channel to maximize the energy distance between the charge carriers in the channel and the defect bands in the amorphous aluminium gate oxide. Charge trapping is highly sensitive to the energetic alignment of the Fermi level of the channel with the defect band in the insulator, and thus, our approach minimizes the amount of electrically active border traps without the need to reduce the total number of traps in the insulator.