3-bit multilevel operation with accurate programming scheme in TiOx/Al2O3memristor crossbar array for quantized neuromorphic system

Threshold learning algorithm for memristive neural network with binary switching behavior

On-chip learning is an effective method for adjusting artificial neural networks in neuromorphic computing systems by considering hardware intrinsic properties. However, it faces challenges due to hardware nonidealities, such as the nonlinearity of potentiation and depression and limitations on fine weight adjustment. In this study, we propose a threshold learning algorithm for a variation-tolerant ternary neural network in a memristor crossbar array. This algorithm utilizes two tightly separated resistance states in memristive devices to represent weight values. The high-resistance state (HRS) and low-resistance state (LRS) defined as read current of < 0.1 μA and > 1 μA, respectively, were successfully programmed in a 32 × 32 crossbar array, and exhibited half-normal distributions due to the programming method. To validate our approach experimentally, a 64 × 10 single-layer fully connected network were trained in the fabricated crossbar for an 8 × 8 MNIST dataset using the threshold learning algorithm, where the weight value is updated when a gradient determined by backpropagation exceeds a threshold value. Thanks to the large margin between the two states of the memristor, we observed only a 0.42 % drop in classification accuracy compared to the baseline network results. The threshold learning algorithm is expected to alleviate the programming burden and be utilized in variation-tolerant neuromorphic architectures.

Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its estimated gradient. Additionally, we adopt a fixed kernel method, where inputs are sequentially applied to a crossbar array with a differential memristor pair scheme, reducing unused cell waste. The binary activation has robust characteristics against device state variations, and a neuron circuit is experimentally demonstrated on a customized breadboard. Thanks to the analogue switching characteristics of the memristor device, the accurate vector-matrix multiplication (VMM) operations can be experimentally demonstrated by combining sequential inputs and the weights obtained through tuning operations in the crossbar array. In addition, the feature images extracted by VMM during the hardware inference operations on 100 test samples are classified, and the classification performance by off-chip training is compared with the software results. Finally, inference results depending on the tolerance are statistically verified through several tuning cycles.

Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing

The progress of artificial intelligence and the development of large-scale neural networks have significantly increased computational costs and energy consumption. To address these challenges, researchers are exploring low-power neural network implementation approaches and neuromorphic computing systems are being highlighted as potential candidates. Specifically, the development of high-density and reliable synaptic devices, which are the key elements of neuromorphic systems, is of particular interest. In this study, an 8 × 16 memcapacitor crossbar array that combines the technological maturity of flash cells with the advantages of NAND flash array structure is presented. The analog properties of the array with high reliability are experimentally demonstrated, and vector-matrix multiplication with extremely low error is successfully performed. Additionally, with the capability of weight fine-tuning characteristics, a spiking neural network for CIFAR-10 classification via off-chip learning at the wafer level is implemented. These experimental results demonstrate a high level of accuracy of 92.11%, with less than a 1.13% difference compared to software-based neural networks (93.24%).

Intrinsic variation effect in memristive neural network with weight quantization

To analyze the effect of the intrinsic variations of the memristor device on the neuromorphic system, we fabricated 32 × 32 Al₂O₃/TiO_x-based memristor crossbar array and implemented 3 bit multilevel conductance as weight quantization by utilizing the switching characteristics to minimize the performance degradation of the neural network. The tuning operation for 8 weight levels was confirmed with a tolerance of ±4μA (±40μS). The endurance and retention characteristics were also verified, and the random telegraph noise (RTN) characteristics were measured according to the weight range to evaluate the internal stochastic variation effect. Subsequently, a memristive neural network was constructed by off-chip training with differential memristor pairs for the Modified National Institute of Standards and Technology (MNIST) handwritten dataset. The pre-trained weights were quantized, and the classification accuracy was evaluated by applying the intrinsic variations to each quantized weight. The intrinsic variations were applied using the measured weight inaccuracy given by the tuning tolerance, RTN characteristics, and the fault device yield. We believe these results should be considered when the pre-trained weights are transferred to a memristive neural network by off-chip training.

Effect of Hydrogen Migration in SiO2/Al2O3 Stacked Gate Insulator of InGaZnO Thin-Film Transistors

In this work, the correlation between SiO2 deposition thickness and hydrogen content is discussed and the effect of the SiO2 layer on the properties of synaptic InGaZnO (IGZO) TFTs is analyzed. Three types of IGZO synaptic thin-film transistors (TFTs) were fabricated with different gate insulators, and the effect of SiO2 as a gate insulator was investigated. XPS analysis confirmed that the hydrogen content in the Al2O3 and SiO2 layers increased during SiO2 deposition step for all depth regions. Hydrogen injected by the SiO2 layer deposition step was confirmed to improve the memory window through more threshold voltage shift under positive bias stress (PBS) and negative bias stress (NBS) conditions. In addition, the retention characteristics were improved due to the low hydrogen movement velocity in the SiO2 layer. These results contribute to the optimization of the amount of hydrogen, and the proposed device has potential as a synaptic device capable of neuromorphic computing.

Architecture and Process Integration Overview of 3D NAND Flash Technologies

In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.