Investigation of charge trapping mechanism in MoS2field effect transistor by incorporating Al into host La2O3as gate dielectric

Low-Power OR Logic Ferroelectric In-Situ Transistor Based on a CuInP2S6/MoS2 Van Der Waals Heterojunction

Due to the limitations of thermodynamics, the Boltzmann distribution of electrons hinders the further reduction of the power consumption of field-effect transistors. However, with the emergence of ferroelectric materials, this problem is expected to be solved. Herein, we demonstrate an OR logic ferroelectric in-situ transistor based on a CIPS/MoS2 Van der Waals heterojunction. Utilizing the electric field amplification of ferroelectric materials, the CIPS/MoS2 vdW ferroelectric transistor offers an average subthreshold swing (SS) of 52 mV/dec over three orders of magnitude, and a minimum SS of 40 mV/dec, which breaks the Boltzmann limit at room temperature. The dual-gated ferroelectric in-situ transistor exhibits excellent OR logic operation with a supply voltage of less than 1 V. The results indicate that the CIPS/MoS2 vdW ferroelectric transistor has great potential in ultra-low-power applications due to its in-situ construction, steep-slope subthreshold swing and low supply voltage.