Atomic layer deposited Al2O3passivation layer for few-layer WS2field effect transistors

Modulated wafer-scale WS2 films based on atomic-layer-deposition for various device applications

Tungsten disulfide (WS2) is promising for potential applications in transistors and gas sensors due to its high mobility and high adsorption of gas molecules onto edge sites. This work comprehensively studied the deposition temperature, growth mechanism, annealing conditions, and Nb doping of WS2 to prepare high-quality wafer-scale N- and P-type WS2 films by atomic layer deposition (ALD). It shows that the deposition and annealing temperature greatly influence the electronic properties and crystallinity of WS2, and insufficient annealing will seriously reduce the switch ratio and on-state current of the field effect transistors (FETs). Besides, the morphologies and carrier types of WS2 films can be controlled by adjusting the processes of ALD. The obtained WS2 films and the films with vertical structures were used to fabricate FETs and gas sensors, respectively. Among them, the Ion/Ioff ratio of N- and P-type WS2 FETs is 105 and 102, respectively, and the response of N- and P-type gas sensors is 14% and 42% under 50 ppm NH3 at room temperature, respectively. We have successfully demonstrated a controllable ALD process to modify the morphology and doping behavior of WS2 films with various device functionalities based on acquisitive characteristics.

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2

In this work, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS₂ and p-MoTe₂ grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO₂ is used as the gate dielectric. An Al₂ O₃ seed layer is used to protect the MoS₂ from heavily n-doping in the later-on atomic layer deposition process. P-MoTe₂ FET is intentionally designed as the upper layer. Because p-doping of MoTe₂ results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe₂ . An HfO₂ capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at V_DD of 1 V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at V_DD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.