Design considerations for effective neural signal sensing and amplification: a review

A linear cross-coupled gate-driven quasi-floating bulk low-power wide input range transconductor

High linearity for a wider input voltage range and low-power operation of the operational transconductance amplifier (OTA) are indispensable parameters for health care applications, which require high quality and accurate signal conditioning. However, achieving low-power operation along with high linearity at low supply voltages is challenging for OTA using conventional low-power and linearization techniques. This paper proposes an OTA based on a cross-coupled gate-driven quasi-floating bulk (CGDQFB) MOSFET and source-degenerated linearization techniques, which works at a supply of ±0.5 V. The post-layout simulations of the proposed OTA are performed in the 180 nm standard CMOS process, which shows a transconductance of 0.321 μS, an output impedance of 331 MΩ, an input impedance of 897 GΩ, a DC gain of 40.54 dB, a gain-bandwidth of 0.145 MHz, a total harmonic distortion (THD) of 51.09 dB for an input voltage range of 626.7 mV at a frequency of 100.39 Hz, and a power consumption of 0.45 μW. The proposed OTA shows an input common mode range of -0.34 to 0.4 V, an output voltage swing of -0.34 to 0.34 V, a common mode rejection ratio of 91.08 dB, and a consumption area of 23 965.92 µm2. Furthermore, with 200 Monte Carlo iterations, the proposed OTA shows variability for gain and THD of 0.003 and 0.036, respectively. The proposed CGDQFB OTA is a suitable contender for conditioning bio-signals used in health care applications.

0.342 nW Class-AB enhanced flipped source follower low pass filter for biomedical applications

Owing to the impact of process voltage and temperature variations, the design of low-power low-pass filters (LPFs) with improved linearity is still one of the most challenging tasks for effective biological signal processing. This paper presents the design of a fourth-order Class-AB enhanced flipped source follower (EFSF) LPF circuit aimed at the detection of electroencephalography signals. The simulated results attained using complementary metal-oxide-semiconductor 180 nm technology node in Cadence Analog Design Environment demonstrate that the EFSF LPF emulates a DC-gain of -88 mdB with a bandwidth of 100 Hz and consumes 0.342 nW power from a supply voltage of 0.5 V. The calculated figure of merit for the proposed filter is 5.983 × 10-15 J with a dynamic range (DR) of 43.54 dB and input-referred noise of 91 µVrms. It consumes an area of 0.0458 mm2. To check the robustness of the proposed filter circuit, we performed Monte Carlo simulations with 200 runs. The statistical results achieved for the DC-gain, DR, and total harmonic distortion of the proposed filter show mean values of -188.09 mdB, 43.10 dB, and -41.85 dB along with standard deviation values of 285.21 mdB, 718.72 mdB, and 4.52 dB, respectively. The proposed Class-AB EFSF LPF can be used to achieve high power efficiency in future low-voltage and low-power biological systems.

Design of a low-noise low-voltage amplifier for improved neural signal recording

Design of amplifier circuits with low-noise operable at low-power to be used, especially for implantable neural interfaces, remains a huge challenge. This research paper presents the design of a low-noise low-voltage neural recording amplifier suitable for amplifying local field potentials and extracellular action potentials so as to meet the end requirement of an implantable neuro-medical system. Critical performance parameters of the smaller circuit blocks of the complete neural amplifier architecture have been found with the help of detailed mathematical analysis and then verified by the simulations conducted using 0.18 µm 4M1P foundry Semi-conductor Laboratory N-well process. The neural amplifier design proposed in this paper passes neural signal of interest with a mid-band gain of 49.9 dB over a bandwidth of 5.3 Hz-8.6 kHz, draws only 11.5 µW of power from ±0.9 V supply voltage, and exhibits an input-referred noise of 2.6 µV_rms with a noise efficiency factor of 2.27. The area consumed by the proposed neural amplifier architecture is 0.192 mm². The complete circuit design carried out in this paper should prove to be useful in equipment for the diagnosis of neurological disorders.

Analysis and Reduction of Nonlinear Distortion in AC-Coupled CMOS Neural Amplifiers with Tunable Cutoff Frequencies

Integrated CMOS neural amplifiers are key elements of modern large-scale neuroelectronic interfaces. The neural amplifiers are routinely AC-coupled to electrodes to remove the DC voltage. The large resistances required for the AC coupling circuit are usually realized using MOSFETs that are nonlinear. Specifically, designs with tunable cutoff frequency of the input high‑pass filter may suffer from excessive nonlinearity, since the gate-source voltages of the transistors forming the pseudoresistors vary following the signal being amplified. Consequently, the nonlinear distortion in such circuits may be high for signal frequencies close to the cutoff frequency of the input filter. Here we propose a simple modification of the architecture of a tunable AC-coupled amplifier, in which the bias voltages V_gs of the transistors forming the pseudoresistor are kept constant independently of the signal levels, what results in significantly improved linearity. Based on numerical simulations of the proposed circuit designed in 180 nm technology we analyze the Total Harmonic Distortion levels as a function of signal frequency and amplitude. We also investigate the impact of basic amplifier parameters—gain, cutoff frequency of the AC coupling circuit, and silicon area—on the distortion and noise performance. The post-layout simulations of the complete test ASIC show that the distortion is very significantly reduced at frequencies near the cutoff frequency, when compared to the commonly used circuits. The THD values are below 1.17% for signal frequencies 1 Hz–10 kHz and signal amplitudes up to 10 mV peak-to-peak. The preamplifier area is only 0.0046 mm² and the noise is 8.3 µV_rms in the 1 Hz–10 kHz range. To our knowledge this is the first report on a CMOS neural amplifier with systematic characterization of THD across complete range of frequencies and amplitudes of neuronal signals recorded by extracellular electrodes.

Design and simulation of pseudo-resistor with extremely high linearity for an improved neural signal recording

Design of a pseudo-resistor (PR) structure based on a bulk driven quasi floating technique is presented, which not only provides a high value of resistance (≈1 TΩ) over a wider voltage swing of -1 V to 1 V, but also displays extremely high linearity. The same is useful for accurate amplification and recording of neural signals for better diagnosis of many chronic diseases. PR design reported in this paper has been simulated in 0.18 µm technology with BSIM3V3 MOS device models in the 6M1P standard process. The proposed PR has been simulated for its accuracy through its use in the design of the neural amplifier with a display of better performance than earlier reported work.