Differentiating Between Alzheimer's Disease and Frontotemporal Dementia Based on the Resting-State Multilayer EEG Network

Frontotemporal dementia (FTD) is frequently misdiagnosed as Alzheimer's disease (AD) due to similar clinical symptoms. In this study, we constructed frequency-based multilayer resting-state electroencephalogram (EEG) networks and extracted representative network features to improve the differentiation between AD and FTD. When compared with healthy controls (HC), AD showed primarily stronger delta-alpha cross-couplings and weaker theta-sigma cross-couplings. Notably, when comparing the AD and FTD groups, we found that the AD exhibited stronger delta-alpha and delta-beta connectivity than the FTD. Thereafter, by extracting the representative network features and then applying these features in the classification between AD and FTD, an accuracy of 81.1% was achieved. Finally, a multivariable linear regressive model was built, based on the differential topologies, and then adopted to predict the scores of the Mini-Mental State Examination (MMSE) scale. Accordingly, the predicted and actual measured scores were indeed significantly correlated with each other ( r = 0.274, p = 0.036). These findings consistently suggest that frequency-based multilayer resting-state networks can be utilized for classifying AD and FTD and have potential applications for clinical diagnosis.

Realization of the conscience mechanism in CMOS implementation of winner-takes-all self-organizing neural networks

This paper presents a complementary metal-oxide-semiconductor (CMOS) implementation of a conscience mechanism used to improve the effectiveness of learning in the winner-takes-all (WTA) artificial neural networks (ANNs) realized at the transistor level. This mechanism makes it possible to eliminate the effect of the so-called ¿dead neurons,¿ which do not take part in the learning phase competition. These neurons usually have a detrimental effect on the network performance, increasing the quantization error. The proposed mechanism comes as part of the analog implementation of the WTA neural networks (NNs) designed for applications to ultralow power portable diagnostic devices for online analysis of ECG biomedical signals. The study presents Matlab simulations of the network's model, discusses postlayout circuit level simulations and includes results of measurement completed for the physical realization of the circuit.

Neural network implementation using bit streams

A new method for the parallel hardware implementation of artificial neural networks (ANNs) using digital techniques is presented. Signals are represented using uniformly weighted single-bit streams. Techniques for generating bit streams from analog or multibit inputs are also presented. This single-bit representation offers significant advantages over multibit representations since they mitigate the fan-in and fan-out issues which are typical to distributed systems. To process these bit streams using ANNs concepts, functional elements which perform summing, scaling, and squashing have been implemented. These elements are modular and have been designed such that they can be easily interconnected. Two new architectures which act as monotonically increasing differentiable nonlinear squashing functions have also been presented. Using these functional elements, a multilayer perceptron (MLP) can be easily constructed. Two examples successfully demonstrate the use of bit streams in the implementation of ANNs. Since every functional element is individually instantiated, the implementation is genuinely parallel. The results clearly show that this bit-stream technique is viable for the hardware implementation of a variety of distributed systems and for ANNs in particular.

A new architecture for digital stochastic pulse-mode neurons based on the voting circuit

This paper presents a new kind of architecture for artificial digital neurons based on the voting circuit, which may be considered an improved version of those presented in literature. Stochastic pulse modulation has been used, where the values of the neuron's inputs are coded in terms of bit probabilities. The resulting activation function closely resembles the logistic sigmoid, with a transition slope that can be selected at the architectural level with no additional hardware requirements. The proposed neuron architecture has been simulated in software. Simulation results confirm that the neuron features a sigmoid transfer characteristic similar to that of conventional voting circuits. The resource occupation of the neuron, as obtained from implementation on reconfigurable platforms, has been estimated to be significantly lower than previous implementations. The theoretical analysis of the neuron's behavior is also presented.

Simultaneous Perturbation Learning Rule for Recurrent Neural Networks and Its FPGA Implementation

Recurrent neural networks have interesting properties and can handle dynamic information processing unlike ordinary feedforward neural networks. However, they are generally difficult to use because there is no convenient learning scheme. In this paper, a recursive learning scheme for recurrent neural networks using the simultaneous perturbation method is described. The detailed procedure of the scheme for recurrent neural networks is explained. Unlike ordinary correlation learning, this method is applicable to analog learning and the learning of oscillatory solutions of recurrent neural networks. Moreover, as a typical example of recurrent neural networks, we consider the hardware implementation of Hopfield neural networks using a field-programmable gate array (FPGA). The details of the implementation are described. Two examples of a Hopfield neural network system for analog and oscillatory targets are shown. These results show that the learning scheme proposed here is feasible.

FPNA: interaction between FPGA and neural computation

Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed, allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.