Equalization for intracortical microstimulation artifact reduction

Advances in Neural Recording and Stimulation Integrated Circuits

In the past few decades, driven by the increasing demands in the biomedical field aiming to cure neurological diseases and improve the quality of daily lives of the patients, researchers began to take advantage of the semiconductor technology to develop miniaturized and power-efficient chips for implantable applications. The emergence of the integrated circuits for neural prosthesis improves the treatment process of epilepsy, hearing loss, retinal damage, and other neurological diseases, which brings benefits to many patients. However, considering the safety and accuracy in the neural prosthesis process, there are many research directions. In the process of chip design, designers need to carefully analyze various parameters, and investigate different design techniques. This article presents the advances in neural recording and stimulation integrated circuits, including (1) a brief introduction of the basics of neural prosthesis circuits and the repair process in the bionic neural link, (2) a systematic introduction of the basic architecture and the latest technology of neural recording and stimulation integrated circuits, (3) a summary of the key issues of neural recording and stimulation integrated circuits, and (4) a discussion about the considerations of neural recording and stimulation circuit architecture selection and a discussion of future trends. The overview would help the designers to understand the latest performances in many aspects and to meet the design requirements better.

A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers

We present a 180-nm CMOS bidirectional neural interface system-on-chip that enables simultaneous recording and stimulation with on-chip stimulus artifact cancelers. The front-end cancellation scheme incorporates a least-mean-square engine that adapts the coefficients of a 2-tap infinite-impulse-response filter to replicate the stimulation artifact waveform and subtract it at the front-end. Measurements demonstrate the efficacy of the canceler in mitigating artifacts up to 700 mVpp and reducing the front-end amplifier saturation recovery time in response to a 2.5 Vpp artifact. Each recording channel houses a pair of adaptive infinite-impulse-response filters, which enable cancellation of the artifacts generated by the simultaneous operation of the 2 on-chip stimulators. The analog front-end consumes 2.5 μW of power per channel, has a maximum gain of 50 dB and a bandwidth of 9.0 kHz with 6.2 μVrms integrated input-referred noise.

Energy-Efficient Integrated Circuit Solutions Toward Miniaturized Closed-Loop Neural Interface Systems

Miniaturized implantable devices play a crucial role in neural interfaces by monitoring and modulating neural activities on the peripheral and central nervous systems. Research efforts toward a compact wireless closed-loop system stimulating the nerve automatically according to the user's condition have been maintained. These systems have several advantages over open-loop stimulation systems such as reduction in both power consumption and side effects of continuous stimulation. Furthermore, a compact and wireless device consuming low energy alleviates foreign body reactions and risk of frequent surgical operations. Unfortunately, however, the miniaturized closed-loop neural interface system induces several hardware design challenges such as neural activity recording with severe stimulation artifact, real-time stimulation artifact removal, and energy-efficient wireless power delivery. Here, we will review recent approaches toward the miniaturized closed-loop neural interface system with integrated circuit (IC) techniques.

A framework for identification of brain network dynamics using a novel binary noise modulated electrical stimulation pattern

Modeling and identification of brain network dynamics is of great importance both for understanding brain function and for closed-loop control of brain states. In this work, we present a multi-input-multi-output (MIMO) linear state-space model (LSSM) to describe the brain network dynamics in response to electrical stimulation. The LSSM maps the parameters of electrical stimulation, such as frequency, amplitude and pulse-width to recorded brain signals such as electrocorticography (ECoG) and electroencephalography (EEG). Effective identification of the LSSM in open-loop stimulation experiments, however, is strongly dependent on the open-loop input stimulation design. We propose a novel input design to accurately identify the LSSM by integrating the concept of binary noise (BN) with practical constraints on stimulation waveforms. The designed input pattern is a pulse train modulated by stochastic BN parameters. We show that this input pattern both satisfies the necessary spectral condition for accurate system identification and can incorporate any desired pulse shape. Using numerical experiments, we show that the quality of identification depends heavily on the input signal pattern and the proposed binary noise modulated pattern achieves satisfactory identification results, reducing the relative estimation error more than 300 times compared with step sequence modulated, single-sinusoid modulated and multi-sinusoids modulated input patterns.