Spiking neuron computation with the time machine

Investigation on the Wilson Neuronal Model: Optimized Approximation and Digital Multiplierless Implementation

Neuromorphic engineering is an essential science field which incorporates the basic aspects of issues together such as: physics, mathematics, electronics, etc. The primary block in the Central Nervous System (CNS) is neurons that have functional roles such as: receiving, processing, and transmitting data in the brain. This paper presents Wilson Multiplierless Neuron (WMN) model which is a modified version of the original model. This model uses power-2 based functions, Look-Up Table (LUT) approach and shifters to apply a multiplierless digital realization leads to overhead costs reduction and increases in the final system frequency. The proposed model specifically follows the original neuron model in case of spiking patterns and also dynamical pathways. To validate the proposed model in digital hardware implementation, the FPGA board (Xilinx Virtex II XC2VP30) can be used. Hardware results show the increasing in the system frequency compared with the original model and other similar papers. Numerical results demonstrate that the proposed system speed-up is 210 MHz that is higher than the original one, 85 MHz. Additionally, the overall saving in FPGA resources for the proposed model is 96.86 % that is more than the original model, 95.13 %. From case study viewpoint for CNS consideration, a network consisting of Wilson neurons, synapses, and astrocytes have been considered to test the controlling effects on LTP and LTD processes for investigating the neuronal diseases (medical approaches) such as Epilepsy.

In-Memory Computing Architectures for Sparse Distributed Memory

This paper presents an energy-efficient and high-throughput architecture for Sparse Distributed Memory (SDM)-a computational model of the human brain [1]. The proposed SDM architecture is based on the recently proposed in-memory computing kernel for machine learning applications called Compute Memory (CM) [2], [3]. CM achieves energy and throughput efficiencies by deeply embedding computation into the memory array. SDM-specific techniques such as hierarchical binary decision (HBD) are employed to reduce the delay and energy further. The CM-based SDM (CM-SDM) is a mixed-signal circuit, and hence circuit-aware behavioral, energy, and delay models in a 65 nm CMOS process are developed in order to predict system performance of SDM architectures in the auto- and hetero-associative modes. The delay and energy models indicate that CM-SDM, in general, can achieve up to 25 × and 12 × delay and energy reduction, respectively, over conventional SDM. When classifying 16 × 16 binary images with high noise levels (input bad pixel ratios: 15%-25%) into nine classes, all SDM architectures are able to generate output bad pixel ratios (Bo) ≤ 2%. The CM-SDM exhibits negligible loss in accuracy, i.e., its Bo degradation is within 0.4% as compared to that of the conventional SDM.