A system verification platform for high-density epiretinal prostheses

A 13.56 MHz Wireless Power Transfer System With Fully Integrated PLL-Based Frequency-Regulated Reconfigurable Duty Control for Implantable Medical Devices

In this paper, a 13.56 MHz wireless power transfer system with transmitter (TX) and receiver (RX) chips is presented. Both TX and RX chips were designed with fully integrated reconfigurable single power stage to realize adaptive power delivery and output voltage regulation. The reconfigurable operation of TX and RX is synchronized and the reconfiguration frequency which could vary with coupling or loading condition is locked by the proposed phase-locked-loop-based on-time duty controller to mitigate the electromagnetic interference. In addition, calibrations for circuit delay and power switch size were implemented in the RX chip to enhance system efficiency further. The system complexity is reduced considerably by removing the successive power stages and off-chip controllers used in previous studies. The TX and RX chips were fabricated in TSMC 0.18 μm CMOS process. The measurement results demonstrated seamless output voltage regulation under an output power range from 4.2 mW to 162 mW and a peak end-to-end efficiency of 70.1%.

Hexagonal Stimulation Digital Controller Design and Verification for Wireless Subretinal Implant Device

Significant progress has been made in the field of micro/nano-retinal implant technologies. However, the high pixel range, power leakage, reliability, and lifespan of retinal implants are still questionable. Active implantable devices are safe, cost-effective, and reliable. Although a device that can meet basic safety requirements set by the Food and Drug Administration and the European Union is reliable for long-term use and provides control on current and voltage parameters, it will be expensive and cannot be commercially successful. This study proposes an economical, fully controllable, and configurable wireless communication system based on field-programmable gated arrays (FPGAs) that were designed with the ability to cope with the issues that arise in retinal implantation. This system incorporates hexagonal biphasic stimulation pulses generated by a digital controller that can be fully controlled using an external transmitter. The integration of two separate domain analog systems and a digital controller based on FPGAs is proposed in this study. The system was also implemented on a microchip and verified using in vitro results.

An Energy-Efficient ASK Demodulator Robust to Power-Carrier-Interference for Inductive Power and Data Telemetry

Wireless power and datatelemetry based on amplitude-shift keying (ASK) modulation over dual inductive links has been widely adopted in biomedical implants. Due to the mutual inductance between the power and data links, the large power-carrier-interference (PCI) will inevitably cause low signal-to-interference ratio (SIR) of the received signal, thereby increasing the bit-error-rate (BER) of the ASK demodulation. In this paper, an innovative high energy-efficient ASK demodulator robust to PCI has been proposed. Thanks to the proposed sampling-and-subtraction (SAS) architecture, the demodulator is capable of withstanding PCI with an amplitude up to 2.5 times as the data carrier without the need for any high-order filters. The prototype has been implemented with 180 nm standard CMOS process, occupying a core area of 0.51 mm ². The experimental results show that with 1 Mbps data rate and 13.56 MHz carrier frequency, the typical BER is less than 1.3×10 ^-3, while the energy efficiency is 280 pJ/bit, showing 7.5× improvement compared to the prior works. The energy-efficient robustness to PCI demonstrates the potential of the technique to be applied to retina prostheses as well as various kinds of ultra-low-power implantable biomedical devices.

A Wireless Power and Data Transfer IC for Neural Prostheses Using a Single Inductive Link With Frequency-Splitting Characteristic

This paper presents a frequency-splitting-based wireless power and data transfer IC that simultaneously delivers power and forward data over a single inductive link. For data transmission, frequency-shift keying (FSK) is utilized because the FSK modulation scheme supports continuous wireless power transmission without disruption of the carrier amplitude. Moreover, the link that manifests the frequency-splitting characteristic due to a close distance between coupled coils provides wide bandwidth for data delivery without degrading the quality factors of the coils. It results in large power delivery, high data rate, and high power transfer efficiency. The presented IC fabricated in a 180-nm BCD process simultaneously achieves up-to-115-mW wireless power delivery to the load and 2.5-Mb/s downlink data rate over the single inductive link. The measured overall power efficiency from the DC power supply at the transmitter module to the load at the receiver module reaches 56.7 % at its maximum, and the bit error rate is lower than 10 ^-6 at 2.5 Mb/s. As a result, the figure of merit (FoM) for data transmission is enhanced by 2 times, and the FoM for power delivery is improved by 38.7 times compared to prior state-of-the-arts using a single inductive link.

13.56 MHz Triple Mode Rectifier Circuit With Extended Coupling Range for Wirelessly Powered Implantable Medical Devices

In this work, a wide input/output range triple mode rectifier circuit operating at 13.56 MHz is implemented to power up medical implants. The proposed novel multi-mode rectifier circuit charges the load for an extended coupling range and eliminates the requirement of alignment magnets. The charging process is achieved in three different modes based on the voltage level of the received signal affected by the distance and the alignment of the inductively coupled coils. Current mode (CM) circuit is activated for loosely coupled coils whereas voltage mode (VM) rectification is proposed for high coupling ratios. Extended coupling range is covered with the activation of half wave rectification mode (HWM) in between CM and VM. The rectifier circuit utilizes these three modes in a single circuit operating at 13.56 MHz according to the receiver signal voltage. The circuit is implemented in TSMC 180 nm BCD technology with 0.9 mm² active area and tested with printed coils. According to the measurements, the circuit operates in the received power range of 4 to 57.7 mW, which corresponds to 0.10-0.42 coupling range. The maximum power conversion efficiency (PCE) of each operation mode is 51.78%, 82.49%, and 89.34% for CM, HWM, and VM, respectively, while charging a 3.3 V load.

Synchronized Biventricular Heart Pacing in a Closed-chest Porcine Model based on Wirelessly Powered Leadless Pacemakers

About 30% of patients with impaired cardiac function have ventricular dyssynchrony and seek cardiac resynchronization therapy (CRT). In this study, we demonstrate synchronized biventricular (BiV) pacing in a leadless fashion by implementing miniaturized and wirelessly powered pacemakers. With their flexible form factors, two pacemakers were implanted epicardially on the right and left ventricles of a porcine model and were inductively powered at 13.56 MHz and 40.68 MHz industrial, scientific, and medical (ISM) bands, respectively. The power consumption of these pacemakers is reduced to µW-level by a novel integrated circuit design, which considerably extends the maximum operating distance. Leadless BiV pacing is demonstrated for the first time in both open-chest and closed-chest porcine settings. The clinical outcomes associated with different interventricular delays are verified through electrophysiologic and hemodynamic responses. The closed-chest pacing only requires the external source power of 0.3 W and 0.8 W at 13.56 MHz and 40.68 MHz, respectively, which leads to specific absorption rates (SARs) 2–3 orders of magnitude lower than the safety regulation limit. This work serves as a basis for future wirelessly powered leadless pacemakers that address various cardiac resynchronization challenges.

A Dual-Output Reconfigurable Shared-Inductor Boost-Converter/Current-Mode Inductive Power Management ASIC With 750% Extended Output-Power Range, Adaptive Switching Control, and Voltage-Power Regulation

This paper describes a dual-output, reconfigurable integrated power management (IPM) ASIC for inductive power delivery. The proposed ASIC operates either as a current-mode (CM) rectifier or a boost converter by sharing the receiver (Rx) coil (LRx) to improve performance of inductive power transmission against the variations of Rx input power (PRx) and dual-output DC power (PL+ PHv). Conventional IPM structures either fail to generate regulated outputs (e.g., VL and VHv) when the required PL+ PHv exceeds PRx or suffer from low power-conversion efficiency (PCE) when PRx exceeds PL+ PHv due to voltage regulation and protection. To overcome these challenges, the proposed ASIC offers the unique capabilities of 1) generating multiple regulated outputs [Formula: see text] directly from LRx with single-stage conversion, 2) efficient CM operation with active rectification, enabled by adaptive switching control (ASC), 3) charging a large capacitor ( CS) with the purpose of operating as a shared-inductor boost converter (SBC), transferring energy from CS to CL and CHv, when , and 4) efficient voltage-power regulation (VPR). A proof-of-concept chip was fabricated in a 0.35-μm 2P4M standard CMOS process occupying 1.35-mm2 active area. In measurements, the proposed ASIC was able to successfully provide regulated [Formula: see text] and [Formula: see text] despite significant variations in PRx, PL, and PHv. Moreover, the chip extended the peak output power range by 750% and improved the PCE by 1.3 times and 8.1 times thanks to the ASC and VPR, respectively.

A Fully Integrated Wireless SoC for Motor Function Recovery After Spinal Cord Injury

This paper presents a wirelessly powered, fully integrated system-on-a-chip (SoC) supporting 160-channel stimulation, 16-channel recording, and 48-channel bio-impedance characterization to enable partial motor function recovery through epidural spinal cord electrical stimulation. A wireless transceiver is designed to support quasi full-duplex data telemetry at a data rate of 2 Mb/s. Furthermore, a unique in situ bio-impedance characterization scheme based on time-domain analysis is implemented to derive the Randles cell electrode model of the electrode-electrolyte interface. The SoC supports concurrent stimulation and recording while the high-density stimulator array meets an output compliance voltage of up to ±10 V with versatile stimulus programmability. The SoC consumes 18 mW and occupies a chip area of 5.7 mm × 4.4 mm using 0.18 μm high-voltage CMOS process. In our in vivo rodent experiment, the SoC is used to perform wireless recording of EMG responses while stimulation is applied to enable the standing and stepping of a paralyzed rat. To facilitate the system integration, a novel thin film polymer packaging technique is developed to provide a heterogeneous integration of the SoC, coils, discrete components, and high-density flexible electrode array, resulting in a miniaturized prototype implant with a weight and form factor of 0.7 g and 0.5 cm3, respectively.

Versatile Stimulation Back-End With Programmable Exponential Current Pulse Shapes for a Retinal Visual Prosthesis

This paper reports on the design, implementation, and test of a stimulation back-end, for an implantable retinal prosthesis. In addition to traditional rectangular pulse shapes, the circuit features biphasic stimulation pulses with both rising and falling exponential shapes, whose time constants are digitally programmable. A class-B second generation current conveyor is used as a wide-swing, high-output-resistance stimulation current driver, delivering stimulation current pulses of up to ±96 μA to the target tissue. Duration of the generated current pulses is programmable within the range of 100 μs to 3 ms. Current-mode digital-to-analog converters (DACs) are used to program the amplitudes of the stimulation pulses. Fabricated using the IBM 130 nm process, the circuit consumes 1.5×1.5 mm² of silicon area. According to the measurements, the DACs exhibit DNL and INL of 0.23 LSB and 0.364 LSB, respectively. Experimental results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance of as high as 25 k Ω. Maximum power consumption of the proposed design is 3.4 mW when delivering biphasic rectangular pulses to the target load. A charge pump block is in charge of the upconversion of the standard 1.2-V supply voltage to ±3.3V.

An On-Chip Multi-Voltage Power Converter With Leakage Current Prevention Using 0.18 μm High-Voltage CMOS Process

In this paper, we present an on-chip multi-voltage power converter incorporating of a quad-voltage timing-control rectifier and regulators to produce ±12 V and ±1.8 V simultaneously through inductive powering. The power converter achieves a PCE of 77.3% with the delivery of more than 100 mW to the implant. The proposed rectifier adopts a two-phase start-up scheme and mixed-voltage gate controller to avoid substrate leakage current. This current cannot be prevented by the conventional dynamic substrate biasing technique when using the high-voltage CMOS process with transistor threshold voltage higher than the turn-on voltage of parasitic diodes. High power conversion efficiency is achieved by 1) substrate leakage current prevention, 2) operating all rectifying transistors as switches with boosted gate control voltages, and 3) compensating the delayed turn-on and preventing reverse leakage current of rectifying switches with the proposed look-ahead comparator. This chip occupies an area of 970 μm × 4500 μm in a 0.18 μ m 32 V HV CMOS process. The quad-voltage timing-control rectifier alone is able to output a high DC voltage at the range of [2.5 V, 25 V]. With this power converter, both bench-top experiment and in-vivo power link test using a rat model were validated.

Visual prostheses: the enabling technology to give sight to the blind

Millions of patients are either slowly losing their vision or are already blind due to retinal degenerative diseases such as retinitis pigmentosa (RP) and age-related macular degeneration (AMD) or because of accidents or injuries. Employment of artificial means to treat extreme vision impairment has come closer to reality during the past few decades. Currently, many research groups work towards effective solutions to restore a rudimentary sense of vision to the blind. Aside from the efforts being put on replacing damaged parts of the retina by engineered living tissues or microfabricated photoreceptor arrays, implantable electronic microsystems, referred to as visual prostheses, are also sought as promising solutions to restore vision. From a functional point of view, visual prostheses receive image information from the outside world and deliver them to the natural visual system, enabling the subject to receive a meaningful perception of the image. This paper provides an overview of technical design aspects and clinical test results of visual prostheses, highlights past and recent progress in realizing chronic high-resolution visual implants as well as some technical challenges confronted when trying to enhance the functional quality of such devices.

Retinal prosthesis

Retinal prosthesis has been translated from the laboratory to the clinic over the past two decades. Currently, two devices have regulatory approval for the treatment of retinitis pigmentosa. These devices provide partial sight restoration and patients use this improved vision in their everyday lives. Improved mobility and object detection are some of the more notable findings from the clinical trials. However, significant vision restoration will require both better technology and improved understanding of the interaction between electrical stimulation and the retina. This paper reviews the recent clinical trials and highlights technology breakthroughs that will contribute to next generation of retinal prostheses.

A fully intraocular high-density self-calibrating epiretinal prosthesis

This paper presents a fully intraocular self-calibrating epiretinal prosthesis with 512 independent channels in 65 nm CMOS. A novel digital calibration technique matches the biphasic currents of each channel independently while the calibration circuitry is shared among every 4 channels. Dual-band telemetry for power and data with on-chip rectifier and clock recovery reduces the number of off-chip components. The rectifier utilizes unidirectional switches to prevent reverse conduction loss in the power transistors and achieves an efficiency > 80%. The data telemetry implements a phase-shift keying (PSK) modulation scheme and supports data rates up to 20 Mb/s. The system occupies an area of 4.5 ×3.1 mm². It features a pixel size of 0.0169 mm² and arbitrary waveform generation per channel. In vitro measurements performed on a Pt/Ir concentric bipolar electrode in phosphate buffered saline (PBS) are presented. A statistical measurement over 40 channels from 5 different chips shows a current mismatch with μ = 1.12 μA and σ = 0.53 μA. The chip is integrated with flexible MEMS origami coils and parylene substrate to provide a fully intraocular implant.

A fully-integrated high-compliance voltage SoC for epi-retinal and neural prostheses

This paper presents a fully functionally integrated 1024-channel mixed-mode and mixed-voltage system-on-a-chip (SoC) for epi-retinal and neural prostheses. Taking an AC input, an integrated power telemetry circuits is capable of generating multiple DC voltages with a voltage conversion efficiency of 83% at a load of 100 mW without external diodes or separate power integrated circuits, reducing the form factor of the prosthetic device. A wireless DPSK receiver with a novel noise reduction scheme supports a data rate of 2 Mb/s at a bit-error-rate of 2 ×10⁻⁷. The 1024-channel stimulator array meets an output compliance voltage of ±10 V and provides flexible stimulation waveforms. Through chip-clustering, the stimulator array can be further expanded to 4096 channels. This SoC is designed and fabricated in TSMC 0.18 μm high-voltage 32 V CMOS process and occupies a chip area of 5.7 mm × 6.6 mm. Using this SoC, a retinal implant bench-top test system is set up with real-time visual verification. In-vitro experiment conducted in artificial vitreous humor is designed and set-up to investigate stimulation waveforms for better visual resolution. In our in-vivo experiment, a hind-limb paralyzed rat with spinal cord transection and implanted chronic epidural electrodes has been shown to regain stepping and standing abilities using stimulus provided by the SoC.