A 13-Channel 1.53-mW 11.28-mm2 Electrical Impedance Tomography SoC Based on Frequency Division Multiplexing for Lung Physiological Imaging

FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation

In principle, the recently proposed capacitive-coupling impedance spectroscopy (CIS) has the capability to acquire frequency spectra of complex electrical impedance sequentially on a millisecond timescale. Even when the measured object with time-varying unknown resistance R_x is capacitively coupled with the measurement electrodes with time-varying unknown capacitance C_x, CIS can be measured. As a proof of concept, this study aimed to develop a prototype that implemented the novel algorithm of CIS and circuit parameter estimation to verify whether the frequency spectra and circuit parameters could be obtained in milliseconds and whether time-varying impedance could be measured. This study proposes a dedicated processor that was implemented as field-programmable gate arrays to perform CIS, estimate R_x and C_x, and their digital-to-analog conversions at a certain time, and to repeat them continually. The proposed processor executed the entire sequence in the order of milliseconds. Combined with a front-end nonsinusoidal oscillator and interfacing circuits, the processor estimated the fixed R_x and fixed C_x with reasonable accuracy. Additionally, the combined system with the processor succeeded in detecting a quick optical response in the resistance of the cadmium sulfide (CdS) photocell connected in series with a capacitor, and in reading out their resistance and capacitance independently as voltages in real-time.

On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material's impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform's frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.

An Impedance Readout IC with Ratio-Based Measurement Techniques for Electrical Impedance Spectroscopy

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 μW for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1°, respectively.

An Energy-Efficient ASK Demodulator Robust to Power-Carrier-Interference for Inductive Power and Data Telemetry

Wireless power and datatelemetry based on amplitude-shift keying (ASK) modulation over dual inductive links has been widely adopted in biomedical implants. Due to the mutual inductance between the power and data links, the large power-carrier-interference (PCI) will inevitably cause low signal-to-interference ratio (SIR) of the received signal, thereby increasing the bit-error-rate (BER) of the ASK demodulation. In this paper, an innovative high energy-efficient ASK demodulator robust to PCI has been proposed. Thanks to the proposed sampling-and-subtraction (SAS) architecture, the demodulator is capable of withstanding PCI with an amplitude up to 2.5 times as the data carrier without the need for any high-order filters. The prototype has been implemented with 180 nm standard CMOS process, occupying a core area of 0.51 mm ². The experimental results show that with 1 Mbps data rate and 13.56 MHz carrier frequency, the typical BER is less than 1.3×10 ^-3, while the energy efficiency is 280 pJ/bit, showing 7.5× improvement compared to the prior works. The energy-efficient robustness to PCI demonstrates the potential of the technique to be applied to retina prostheses as well as various kinds of ultra-low-power implantable biomedical devices.

Multi-Channel Biopotential Acquisition System Using Frequency-Division Multiplexing With Cable Motion Artifact Suppression

A multi-channel, CMOS-based biopotential acquisition system is presented that uses amplitude modulated, frequency division multiplexing (AM-FDM) to decrease wire count and provide resilience against motion artifacts and cable noise. Differential active electrode (AE) pairs capture surface biopotential signals, each modulated by a different carrier frequency and combined via current-domain summing. The presented approach requires only a single wire for signal transmission between AEs and back-end readout, along with clock and ground wires, to support multiple active electrodes using a 3-wire cable. Frequency modulation prior to transmission mitigates the effect of low-frequency cable motion artifacts and 50/60 Hz mains interference in the cable. A prototype FDM-based biopotential acquisition system was implemented in a 180 nm CMOS process, including a four-channel front-end active electrode IC for signal conditioning and modulation, and a back-end IC for demodulation and digitization. Each channel occupies 0.75 mm [Formula: see text] and consumes 43.8 μ W, inclusive of ADC power. Using both AE and BE ICs, a four-channel biopotential recording system is demonstrated using a 3-wire interface, where the system achieves attenuation of low-frequency cable motion artifacts by 15X and 60 Hz mains noise coupled into the cable by 62X.

A Polar-Demodulation-Based Impedance-Measurement IC Using Frequency-Shift Technique With Low Power Consumption and Wide Frequency Range

In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18- μm CMOS technology consumes the power of 756 μW while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1 % and 1.9 ^°, respectively.

An Imaged Based Method for Universal Performance Evaluation of Electrical Impedance Tomography Systems

This paper describes a simple and reproducible method for universal evaluation of the performance of electrical impedance tomography (EIT) systems using reconstructed images. To address the issues where common electrical parameters are not directly related to the quality of EIT images, based on objective full reference (FR) image quality assessment, the method provides a visually distinguishable hot colormap and two new FR metrics, the global and the more specific 'region of interest'. A passive 16 electrode EIT system using an application specific integrated circuit front-end was used to evaluate the proposed method. The measured results show, both visually and in terms of the proposed FR metrics, the impact on recorded EIT images with different design parameters and non-idealities. The paper also compares the image results of a passive electrode system with a matched 'single variable' active electrode system and demonstrates the merit of an active electrode system for noise interference. A figure of merit based on the FR metrics is proposed.

A 108 dB DR Δ∑-∑M Front-End With 720 mVpp Input Range and >±300 mV Offset Removal for Multi-Parameter Biopotential Recording

The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2^nd-order hybrid-CTDT Δ∑-∑ modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional Δ∑ modulator, while employing an extra ∑-stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18-μm CMOS process and achieves a peak SNR of 105.6 dB and a dynamic range of 108.3 dB, for a maximum input range of 720 mV_pp. The measured input-referred noise is 0.98 μV_rms over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.

Time Stamp - A Novel Time-to-Digital Demodulation Method for Bioimpedance Implant Applications

Bioimpedance analysis is a noninvasive and inexpensive technology used to investigate the electrical properties of biological tissues. The analysis requires demodulation to extract the real and imaginary parts of the impedance. Conventional systems use complex architectures such as I-Q demodulation. In this paper, a very simple alternative time-to-digital demodulation method or 'time stamp' is proposed. It employs only three comparators to identify or stamp in the time domain, the crossing points of the excitation signal, and the measured signal. In a CMOS proof of concept design, the accuracy of impedance magnitude and phase is 97.06% and 98.81% respectively over a bandwidth of 10 kHz to 500 kHz. The effect of fractional-N synthesis is analysed for the counter-based zero crossing phase detector obtaining a finer phase resolution (0.51˚ at 500 kHz) using a counter clock frequency ( f_clk = 12.5 MHz). Because of its circuit simplicity and ease of transmitting the time stamps, the method is very suited to implantable devices requiring low area and power consumption.