An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces

A 512-Ch Dual-Mode Microchip for Simultaneous Measurements of Electrophysiological and Neurochemical Activities

In the study of the brain, large and high-density microelectrode arrays have been widely used to study the behavior of neurotransmission. CMOS technology has facilitated these devices by enabling the integration of high-performance amplifiers directly on-chip. Usually, these large arrays measure only the voltage spikes resulting from action potentials traveling along firing neuronal cells. However, at synapses, communication between neurons occurs by the release of neurotransmitters, which cannot be measured on typical CMOS electrophysiology devices. Development of electrochemical amplifiers has resulted in the measurement of neurotransmitter exocytosis down to the level of a single vesicle. To effectively monitor the complete picture of neurotransmission, measurement of both action potentials and neurotransmitter activity is needed. Current efforts have not resulted in a device that is capable of the simultaneous measurement of action potential and neurotransmitter release at the same spatiotemporal resolution needed for a comprehensive study of neurotransmission. In this paper, we present a true dual-mode CMOS device that fully integrates 256-ch electrophysiology amplifiers and 256-ch electrochemical amplifiers, along with an on-chip 512 electrode microelectrode array capable of simultaneous measurement from all 512 channels.

Power Budget of a Skull Unit in a Fully-Implantable Brain-Computer Interface: Bio-Heat Model

The aim of this study is to estimate the maximum power consumption that guarantees the thermal safety of a skull unit (SU). The SU is part of a fully-implantable bi-directional brain computer-interface (BD-BCI) system that aims to restore walking and leg sensation to those with spinal cord injury (SCI). To estimate the SU power budget, we created a bio-heat model using the finite element method (FEM) implemented in COMSOL. To ensure that our predictions were robust against the natural variation of the model's parameters, we also performed a sensitivity analysis. Based on our simulations, we estimated that the SU can nominally consume up to 70 mW of power without raising the surrounding tissues' temperature above the thermal safety threshold of 1°C. When considering the natural variation of the model's parameters, we estimated that the power budget could range between 47 and 81 mW. This power budget should be sufficient to power the basic operations of the SU, including amplification, serialization and A/D conversion of the neural signals, as well as control of cortical stimulation. Determining the power budget is an important specification for the design of the SU and, in turn, the design of a fully-implantable BD-BCI system.

A Fully-Integrated 1µW/Channel Dual-Mode Neural Data Acquisition System for Implantable Brain-Machine Interfaces

This paper presents an ultra-low power mixed-signal neural data acquisition (MSN-DAQ) system that enables a novel low-power hybrid-domain neural decoding architecture for implantable brain-machine interfaces with high channel count. Implemented in 180nm CMOS technology, the 32-channel custom chip operates at 1V supply voltage and achieves excellent performance including 1.07µW/channel, 2.37/5.62 NEF/PEF and 88dB common-mode rejection ratio (CMRR) with significant back-end power-saving advantage compared to prior works. The fabricated prototype was further evaluated with in vivo human tests at bedside, and its performance closely follows that of a commercial recording system.

A 1024-Channel 10-Bit 36- μW/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping

This paper presents a 1024-channel neural read-out integrated circuit (ROIC) for solution-gated GFET sensing probes in massive μECoG brain mapping. The proposed time-domain multiplexing of GFET-only arrays enables low-cost and scalable hybrid headstages. Low-power CMOS circuits are presented for the GFET analog frontend, including a CDS mechanism to improve preamplifier noise figures and 10-bit 10-kS/s A/D conversion. The 1024-channel ROIC has been fabricated in a standard 1.8-V 0.18- μm CMOS technology with 0.012 mm ² and 36 μ W per channel. An automated methodology for the in-situ calibration of each GFET sensor is also proposed. Experimental ROIC tests are reported using a custom FPGA-based μECoG headstage with 16×32 and 32×32 GFET probes in saline solution and agar substrate. Compared to state-of-art neural ROICs, this work achieves the largest scalability in hybrid platforms and it allows the recording of infra-slow neural signals.

A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers

We present a 180-nm CMOS bidirectional neural interface system-on-chip that enables simultaneous recording and stimulation with on-chip stimulus artifact cancelers. The front-end cancellation scheme incorporates a least-mean-square engine that adapts the coefficients of a 2-tap infinite-impulse-response filter to replicate the stimulation artifact waveform and subtract it at the front-end. Measurements demonstrate the efficacy of the canceler in mitigating artifacts up to 700 mVpp and reducing the front-end amplifier saturation recovery time in response to a 2.5 Vpp artifact. Each recording channel houses a pair of adaptive infinite-impulse-response filters, which enable cancellation of the artifacts generated by the simultaneous operation of the 2 on-chip stimulators. The analog front-end consumes 2.5 μW of power per channel, has a maximum gain of 50 dB and a bandwidth of 9.0 kHz with 6.2 μVrms integrated input-referred noise.

Thermal Analysis of a Skull Implant in Brain-Computer Interfaces

The goal of this study is to estimate the thermal impact of a titanium skull unit (SU) implanted on the exterior aspect of the human skull. We envision this unit to house the front-end of a fully implantable electrocorticogram (ECoG)-based bi-directional (BD) brain-computer interface (BCI). Starting from the bio-heat transfer equation with physiologically and anatomically constrained tissue parameters, we used the finite element method (FEM) implemented in COMSOL to build a computational model of the SU's thermal impact. Based on our simulations, we predicted that the SU could consume up to 75 mW of power without raising the temperature of surrounding tissues above the safe limits (increase in temperature of 1°C). This power budget by far exceeds the power consumption of our front-end prototypes, suggesting that this design can sustain the SU's ability to record ECoG signals and deliver cortical stimulation. These predictions will be used to further refine the existing SU design and inform the design of future SU prototypes.