A 108 dB DR Δ∑-∑M Front-End With 720 mVpp Input Range and >±300 mV Offset Removal for Multi-Parameter Biopotential Recording

A Novel In-Home Sleep Monitoring System Based on Fully Integrated Multichannel Front-End Chip and Its Multilevel Analyses

OBJECTIVE

A novel in-home sleep monitoring system with an 8-channel biopotential acquisition front-end chip is presented and validated via multilevel data analyses and comparision with advanced polysomnography.

METHODS AND PROCEDURES

The chip includes a cascaded low-noise programmable gain amplifier (PGA) and 24-bit [Formula: see text]-[Formula: see text] analog-to-digital converter (ADC). The PGA is based on three op-amp structure while the ADC adopts cascade of integrator feedforward and feedback (CIFF-B) architecture. An innovative chopper-modulated input-scaling-down technique enhances the dynamic range. The proposed system and commercial polysomnography were used for in-home sleep monitoring of 20 healthy participants. The consistency and significance of the two groups' data were analyzed.

RESULTS

Fabricated in 180 nm BCD technology, the input-referred noise, input impedance, common-mode rejection ratio, and dynamic range of the acquisition front-end chip were [Formula: see text]Vpp, 1.25 GN), 113.9 dB, and 119.8 dB. The kappa coefficients between the sleep stage labels of the three scorers were 0.80, 0.76, and 0.79. The consistency of the slowing index, multiscale entropy, and percentile features between the two devices reached 0.958, 0.885, and 0.834. The macro sleep architecture characteristics of the two devices were not significantly different (all p [Formula: see text] 0.05).

CONCLUSION

The proposed chip was applied to develop an in-home sleep monitoring system with significantly reduced size, power, and cost. Multilevel analyses demonstrated that this system collects stable and accurate in-home sleep data.

CLINICAL IMPACT

The proposed system can be applied for long-term in-home sleep monitoring outside of laboratory environments and sleep disorders screening that with low cost.

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop

This article presents a direct digitizing neural recorder that uses a body-induced offset based DC servo loop to cancel electrode offset (EDO) on-chip. The bulk of the input pair is used to create an offset, counteracting the EDO. The architecture does not require AC coupling capacitors which enables the use of chopping without impedance boosting while maintaining a large input impedance of 238 M Ω over the whole 10 kHz bandwidth. Implemented in a 180 nm HV-CMOS process, the prototype occupies a silicon area of only 0.02 mm² while consuming 12.8 μW and achieving 1.82 μV[Formula: see text] of input-referred noise in the local field potential (LFP) band and a NEF of 5.75.