A 2.66 µW Clinician-Like Cardiac Arrhythmia Watchdog Based on P-QRS-T for Wearable Applications

A 36-nW Electrocardiogram Anomaly Detector Based on a 1.5-bit Non-Feedback Delta Quantizer for Always-on Cardiac Monitoring

An always-on electrocardiogram (ECG) anomaly detector (EAD) with ultra-low power (ULP) consumption is proposed for continuous cardiac monitoring applications. The detector is featured with a 1.5-bit non-feedback delta quantizer (DQ) based feature extractor, followed by a multiplier-less convolutional neural network (CNN) engine, which eliminates the traditional high-resolution analog-to-digital converter (ADC) in conventional signal processing systems. The DQ uses a computing-in-capacitor (CIC) subtractor to quantize the sample-to-sample difference of ECG signal into 1.5-bit ternary codes, which is insensitive to low-frequency baseline wandering. The subsequent event-driven classifier is composed of a low-complexity coarse detector and a systolic-array-based CNN engine for ECG anomaly detection. The DQ and the digital CNN are fabricated in 65-nm and 180-nm CMOS technology, respectively, and the two chips are integrated on board through wire bonding. The measured detection accuracy is 90.6% ∼ 91.3% when tested on the MIT-BIH arrhythmia database, identifying three different ECG anomalies. Operating at 1 V and 1.4 V power supplies for the DQ and the digital CNN, respectively, the measured long-term average power consumption of the core circuits is 36 nW, which makes the detector among those state-of-the-art always-on cardiac anomaly detection devices with the lowest power consumption.

Second-Order Level-Crossing Sampling Analog to Digital Converter for Electrocardiogram Delineation and Premature Ventricular Contraction Detection

This article presents an electrocardiogram (ECG) delineation and arrhythmia heartbeat detection system using a novel second-order level-crossing sampling analog to digital converter (ADC) for real-time data compression and feature extraction. The proposed system consists of the front-end integrated circuit of the data converter, the delineation algorithm, and the arrhythmia detection algorithm. Compared with conventional level-sampling ADCs, the proposed circuit updates tracking thresholds using linear extrapolation, which forms a second-order level-crossing sampling ADC that has sloped sampling levels. The computing is done digitally and is implemented by modifying the digital control logic of a conventional Successive-approximation-register (SAR) ADC. The system separates the sampling and quantization processes and only selects the turning points in the input waveform for quantization. The output of the proposed data converter consists of both the digital value of the selected sampling points and the timestamp between the selected sampling points. The main advantages are data savings for the data converter and the following digital signal processing or communication circuits, which are ideal for low-power sensors. The test chip was fabricated using a 180 nm CMOS process. When sensing sparse signals such as ECG signals the proposed ADC achieves a compression factor of 8.33. The delineation algorithm uses a triangle filter method to locate the fiducial points and measures the intervals, slopes, and morphology of the QRS complex and the P/T waves. Those extracted features are then used in the arrhythmia heartbeat detection algorithm to identify Premature Ventricular Contraction (PVC). The overall performance of the system is evaluated using the MIT-BIH database and the QT database, which is also compared with the recently reported systems. The accuracy, sensitivity, specificity, PPV, and F1 score are 97.3%, 89.6%, 97.8%, 73.3%, and 0.81 for detecting PVC.