An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

Calibration for Sample-And-Hold Mismatches in M-Channel TIADCs Based on Statistics

Time-interleaved analog-to-digital converter (TIADC) is a good option for high sampling rate applications. However, the inevitable sample-and-hold (S/H) mismatches between channels incur undesirable error and then affect the TIADC’s dynamic performance. Several calibration methods have been proposed for S/H mismatches which either need training signals or have less extensive applicability for different input signals and different numbers of channels. This paper proposes a statistics-based calibration algorithm for S/H mismatches in M-channel TIADCs. Initially, the mismatch coefficients are identified by eliminating the statistical differences between channels. Subsequently, the mismatch-induced error is approximated by employing variable multipliers and differentiators in several Richardson iterations. Finally, the error is subtracted from the original output signal to approximate the expected signal. Simulation results illustrate the effectiveness of the proposed method, the selection of key parameters and the advantage to other methods.

Mismatch error correction for time interleaved analog-to-digital converter over a wide frequency range

High-speed high-resolution analog-to-digital conversion is the key part for waveform digitization in physics experiments and many other domains. This paper presents a new fully digital correction of mismatch errors among the channels in Time Interleaved Analog-to-Digital Converter (TIADC) systems. We focus on correction with wide-band input signals, which means that we can correct the mismatch errors for any frequency point in a broad band with only one set of filter coefficients. Studies were also made to show how to apply the correction algorithm beyond the base band, i.e., other Nyquist zones in the under-sampling situation. The structure of the correction algorithm is presented in this paper, as well as simulation results. To evaluate the correction performance, we actually conducted a series of tests with two TIADC systems. The results indicate that the performance of both TIADC systems can be greatly improved by correction, and the effective number of bits is successfully improved to be better than 9.5 bits and 5.5 bits for an input signal up to the bandwidth (-3 dB) range in the 1.6-Gsps 14-bit and the 10-Gsps 8-bit TIADC systems, respectively. Tests were also conducted for input signal frequencies in the second Nyquist zone, which shows that the correction algorithms also work well as expected.

Estimation of channel mismatches in time-interleaved analog-to-digital converters based on fractional delay and sine curve fitting

This paper proposes an algorithm to estimate the channel mismatches in time-interleaved analog-to-digital converter (TIADC) based on fractional delay (FD) and sine curve fitting. Choose one channel as the reference channel and apply FD to the output samples of reference channel to obtain the ideal samples of non-reference channels with no mismatches. Based on least square method, the sine curves are adopted to fit the ideal and the actual samples of non-reference channels, and then the mismatch parameters can be estimated by comparing the ideal sine curves and the actual ones. The principle of this algorithm is simple and easily understood. Moreover, its implementation needs no extra circuits, lowering the hardware cost. Simulation results show that the estimation accuracy of this algorithm can be controlled within 2%. Finally, the practicability of this algorithm is verified by the measurement results of channel mismatch errors of a two-channel TIADC prototype.