Continuous Time Level Crossing Sampling ADC for Bio-Potential Recording Systems

An electronic neuromorphic system for real-time detection of high frequency oscillations (HFO) in intracranial EEG

The analysis of biomedical signals for clinical studies and therapeutic applications can benefit from embedded devices that can process these signals locally and in real-time. An example is the analysis of intracranial EEG (iEEG) from epilepsy patients for the detection of High Frequency Oscillations (HFO), which are a biomarker for epileptogenic brain tissue. Mixed-signal neuromorphic circuits offer the possibility of building compact and low-power neural network processing systems that can analyze data on-line in real-time. Here we present a neuromorphic system that combines a neural recording headstage with a spiking neural network (SNN) processing core on the same die for processing iEEG, and show how it can reliably detect HFO, thereby achieving state-of-the-art accuracy, sensitivity, and specificity. This is a first feasibility study towards identifying relevant features in iEEG in real-time using mixed-signal neuromorphic computing technologies.

Power Efficiency Comparison of Event-Driven and Fixed-Rate Signal Conversion and Compression for Biomedical Applications

Energy-constrained biomedical recording systems need power-efficient data converters and good signal compression in order to meet the stringent power consumption requirements of many applications. In literature today, typically a SAR ADC in combination with digital compression is used. Recently, alternative event-driven sampling techniques have been proposed that incorporate compression in the ADC, such as level-crossing A/D conversion. This paper describes the power efficiency analysis of such level-crossing ADC (LCADC) and the traditional fixed-rate SAR ADC with simple compression. A model for the power consumption of the LCADC is derived, which is then compared to the power consumption of the SAR ADC with zero-order hold (ZOH) compression for multiple biosignals (ECG, EMG, EEG, and EAP). The LCADC is more power efficient than the SAR ADC up to a cross-over point in quantizer resolution (for example 8 bits for an EEG signal). This cross-over point decreases with the ratio of the maximum to average slope in the signal of the application. It also changes with the technology and design techniques used. The LCADC is thus suited for low to medium resolution applications. In addition, the event-driven operation of an LCADC results in fewer data to be transmitted in a system application. The event-driven LCADC without timer and with single-bit quantizer achieves a reduction in power consumption at system level of two orders of magnitude, an order of magnitude better than the SAR ADC with ZOH compression. At system level, the LCADC thus offers a big advantage over the SAR ADC.

Asynchronous Event-driven Encoder With Simultaneous Temporal Envelope and Phase Extraction for Cochlear Implants

Conventional cochlear implants using periodic sampling are power consuming and incapable of capturing the amplitude and phase of the input acoustic signal simultaneously. This paper presents an asynchronous event-driven encoder chip for cochlear implants capable of extracting the temporal fine structure. The chip architecture is based on asynchronous delta modulation (ADM) where the signal peak/trough crossing events are captured and digitized intrinsically, which has the advantages of significantly reduced power consumption, reduced circuit area, and the elimination of dedicated data compression circuitry. An 8-channel prototype chip was fabricated in 0.18 μm 1P6M CMOS process, occupying an area of 0.125 × 1.7 mm² and has a power consumption of 36.2 μW from a 0.6V supply. A 16-channel stimulation encoding system was built by integrating two test chips, capable of processing the entire audible frequency range from 100 Hz to 10 kHz. Experimental characterization using the human voice is provided to corroborate functionality in the application environment.

Event-Driven ECG Sensor in Healthcare Devices for Data Transfer Optimization

The long-term monitoring of cardiovascular signs requires a wearable and connected electrocardiogram (ECG) healthcare device. It increases user's comfort and diagnosis quality of chronic cardiac and/or high-risk patients. This paper covers the enormous data to be transmitted from the ECG device to the physician's, namely the cardiologist's, control unit. Existent ECG devices uniformly sample analog signals and convert them to digital samples which are compressed before data transmission. However, event-driven sampling simultaneously compresses and samples. Therefore, this paper quantitatively compares successive approximation register analog-to-digital converter (SAR ADC) with discrete wavelet transform (DWT) compression and level-crossing analog-to-digital converter (LC-ADC). Evaluation metrics are the percent root-mean-square difference ( PRD ), bit compression ratio ( BCR ) and data length in bits. When a 12-bit reconstruction is operated on the outputs of an 8-bit LC-ADC with 12-bit and 10-kHz reference counter, the BCR is equal to 80% for 75% of test ECG signals. That is better than the 71.87% BCR of the 12-bit 1-kHz SAR ADC with DWT compression. The modeled LC-ADC guarantees a signal quality in terms of PRD comparable to the PRD of the SAR ADC with DWT compression. The data length in bits of the LC-ADC is lower than the data length in bits of the SAR ADC with more than 14-bit resolution with DWT compression for 82% of the test ECG signals. However, for lower resolutions, to obtain lower power consumption for radiofrequency transmission, a better alternative remains the SAR ADC with DWT compression.

A Real-Time Arrhythmia Heartbeats Classification Algorithm Using Parallel Delta Modulations and Rotated Linear-Kernel Support Vector Machines

Real-time wearable electrocardiogram monitoring sensor is one of the best candidates in assisting cardiovascular disease diagnosis. In this paper, we present a novel real-time machine learning system for Arrhythmia classification. The system is based on the parallel Delta modulation and QRS/PT wave detection algorithms. We propose a patient dependent rotated linear-kernel support vector machine classifier that combines the global and local classifiers, with three types of feature vectors extracted directly from the Delta modulated bit-streams. The performance of the proposed system is evaluated using the MIT-BIH Arrhythmia database. According to the AAMI standard, two binary classifications are performed and evaluated, which are supraventricular ectopic beat (SVEB) versus the rest four classes, and ventricular ectopic beat (VEB) versus the rest. For SVEB classification, the preferred SkP-32 method's F1 score, sensitivity, specificity, and positive predictivity value are 0.83, 79.3%, 99.6%, and 88.2%, respectively, and for VEB classification, the numbers are 0.92%, 92.8%, 99.4%, and 91.6%, respectively. The results show that the performance of our proposed approach is comparable to that of published research. The proposed low-complexity algorithm has the potential to be implemented as an on-sensor machine learning solution.

Continuous-Time Acquisition of Biosignals Using a Charge-Based ADC Topology

This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of 5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35  CMOS technology occupying a compact footprint of 0.12 mm². Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75  W from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.

LIF and Simplified SRM Neurons Encode Signals Into Spikes via a Form of Asynchronous Pulse Sigma-Delta Modulation

We show how two spiking neuron models encode continuous-time signals into spikes (action potentials, time-encoded pulses, or point processes) using a special form of sigma-delta modulation (SDM). In particular, we show that the well-known leaky integrate-and-fire (LIF) neuron and the simplified spike response model (SRM₀) neuron encode the continuous-time signals into spikes via a proposed asynchronous pulse SDM (APSDM) scheme. The encoder is clock free using level-crossing sampling with a single-level quantizer, unipolar signaling, differential coding, and pulse-shaping filters. The decoder, in the form of a low-pass filter or bandpass smoothing filter, can be fed with the spikes to reconstruct an estimate of the signal. The density of the spikes reflects the amplitude of the encoded signal. Numerical examples illustrating the concepts and the signaling efficiency of APSDM vis-à-vis SDM for comparable reconstruction accuracies are presented. We anticipate these results will facilitate the design of spiking neurons and spiking neural networks as well as cross fertilizations between the fields of neural coding and the SDM.

Pseudo Asynchronous Level Crossing adc for ecg Signal Acquisition

A new pseudo asynchronous level crossing analogue-to-digital converter (adc) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing adc designs, the proposed design has no digital-to-analogue converter (dac) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed adc was implemented in [Formula: see text] complementary metal-oxide-semiconductor (cmos) technology, the hardware occupies a chip area of 0.0372 mm² and operates from a supply voltage of [Formula: see text] to [Formula: see text]. The adc's power consumption is as low as 0.6 μW with signal bandwidth from [Formula: see text] to [Formula: see text] and achieves an equivalent number of bits (enob) of up to 8 bits.

A Neuromorphic Event-Based Neural Recording System for Smart Brain-Machine-Interfaces

Neural recording systems are a central component of Brain-Machince Interfaces (BMIs). In most of these systems the emphasis is on faithful reproduction and transmission of the recorded signal to remote systems for further processing or data analysis. Here we follow an alternative approach: we propose a neural recording system that can be directly interfaced locally to neuromorphic spiking neural processing circuits for compressing the large amounts of data recorded, carrying out signal processing and neural computation to extract relevant information, and transmitting only the low-bandwidth outcome of the processing to remote computing or actuating modules. The fabricated system includes a low-noise amplifier, a delta-modulator analog-to-digital converter, and a low-power band-pass filter. The bio-amplifier has a programmable gain of 45-54 dB, with a Root Mean Squared (RMS) input-referred noise level of 2.1 μV, and consumes 90 μW . The band-pass filter and delta-modulator circuits include asynchronous handshaking interface logic compatible with event-based communication protocols. We describe the properties of the neural recording circuits, validating them with experimental measurements, and present system-level application examples, by interfacing these circuits to a reconfigurable neuromorphic processor comprising an array of spiking neurons with plastic and dynamic synapses. The pool of neurons within the neuromorphic processor was configured to implement a recurrent neural network, and to process the events generated by the neural recording system in order to carry out pattern recognition.

A 300-mV 220-nW event-driven ADC with real-time QRS detection for wearable ECG sensors

This paper presents an ultra-low-power event-driven analog-to-digital converter (ADC) with real-time QRS detection for wearable electrocardiogram (ECG) sensors in wireless body sensor network (WBSN) applications. Two QRS detection algorithms, pulse-triggered (PUT) and time-assisted PUT (t-PUT), are proposed based on the level-crossing events generated from the ADC. The PUT detector achieves 97.63% sensitivity and 97.33% positive prediction in simulation on the MIT-BIH Arrhythmia Database. The t-PUT improves the sensitivity and positive prediction to 97.76% and 98.59% respectively. Fabricated in 0.13 μm CMOS technology, the ADC with QRS detector consumes only 220 nW measured under 300 mV power supply, making it the first nanoWatt compact analog-to-information (A2I) converter with embedded QRS detector.

An ECG recording front-end with continuous-time level-crossing sampling

An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.