Analysis and compensation of the effects of analog VLSI arithmetic on the LMS algorithm

Application of LMS-Based NN Structure for Power Quality Enhancement in a Distribution Network Under Abnormal Conditions

This paper proposes an application of a least mean-square (LMS)-based neural network (NN) structure for the power quality improvement of a three-phase power distribution network under abnormal conditions. It uses a single-layer neuron structure for the control in a distribution static compensator (DSTATCOM) to attenuate the harmonics such as noise, bias, notches, dc offset, and distortion, injected in the grid current due to connection of several nonlinear loads. This admittance LMS-based NN structure has a simple architecture which reduces the computational complexity and burden which makes it easy to implement. A DSTATCOM is a custom power device which performs various functionalities such as harmonics attenuation, reactive power compensation, load balancing, zero voltage regulation, and power factor correction. Other main contribution of this paper involves operation of the system under abnormal conditions of distribution network which means noise and distortion in voltage and imbalance in three-phase voltages at the point of interconnection. For substantiating and demonstrating the performance of proposed control approach, simulations are carried on MATLAB/Simulink software and corresponding experimental tests are conducted on a developed prototype in the laboratory.

Synchronization Control of Neural Networks With State-Dependent Coefficient Matrices

This brief is concerned with synchronization control of a class of neural networks with state-dependent coefficient matrices. Being different from the existing drive-response neural networks in the literature, a novel model of drive-response neural networks is established. The concepts of uniformly ultimately bounded (UUB) synchronization and convex hull Lyapunov function are introduced. Then, by using the convex hull Lyapunov function approach, the UUB synchronization design of the drive-response neural networks is proposed, and a delay-independent control law guaranteeing the bounded synchronization of the neural networks is constructed. All present conditions are formulated in terms of bilinear matrix inequalities. By comparison, it is shown that the neural networks obtained in this brief are less conservative than those ones in the literature, and the bounded synchronization is suitable for the novel drive-response neural networks. Finally, an illustrative example is given to verify the validity of the obtained results.

Artificial Electrical Morris-Lecar Neuron

In this paper, an experimental electronic neuron based on a complete Morris-Lecar model is presented, which is able to become an experimental unit tool to study collective association of coupled neurons. The circuit design is given according to the ionic currents of this model. The experimental results are compared with the theoretical prediction, leading to a good agreement between them, which therefore validate the circuit. The use of some parts of the circuit is also possible for other neurons models, namely for those based on ionic currents.

Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition

Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods.

Noise-shaping gradient descent-based online adaptation algorithms for digital calibration of analog circuits

Analog circuits that are calibrated using digital-to-analog converters (DACs) use a digital signal processor-based algorithm for real-time adaptation and programming of system parameters. In this paper, we first show that this conventional framework for adaptation yields suboptimal calibration properties because of artifacts introduced by quantization noise. We then propose a novel online stochastic optimization algorithm called noise-shaping or ΣΔ gradient descent, which can shape the quantization noise out of the frequency regions spanning the parameter adaptation trajectories. As a result, the proposed algorithms demonstrate superior parameter search properties compared to floating-point gradient methods and better convergence properties than conventional quantized gradient-methods. In the second part of this paper, we apply the ΣΔ gradient descent algorithm to two examples of real-time digital calibration: 1) balancing and tracking of bias currents, and 2) frequency calibration of a band-pass Gm-C biquad filter biased in weak inversion. For each of these examples, the circuits have been prototyped in a 0.5-μm complementary metal-oxide-semiconductor process, and we demonstrate that the proposed algorithm is able to find the optimal solution even in the presence of spurious local minima, which are introduced by the nonlinear and non-monotonic response of calibration DACs.