Computationally efficient neural feature extraction for spike sorting in implantable high-density recording systems

Spike Sorting of Non-Stationary Data in Successive Intervals Based on Dirichlet Process Mixtures

This paper proposes a new automatic method for spike sorting and tracking non-stationary data based on the Dirichlet Process Mixture (DPM). Data is divided into non-overlapping intervals and mixtures are applied to individual frames rather than to the whole data. In this paper, we have used the information of the previous frame to estimate the cluster parameters of the current interval. Specifically, the means of the clusters in the previous frame are used for estimating the cluster means of the current one, and other parameters are estimated via noninformative priors. The proposed method is capable to track variations in size, shape, or location of clusters as well as detecting the appearance and disappearance of them. We present results in two-dimensional space of first and second principal components (PC1-PC2), but any other feature extraction method leading to the ability of modeling spikes with Normal or t-Student distributions can also be applied. Application of this approach to simulated data and the recordings from anesthetized rat hippocampus confirms its superior performance in comparison to a standard DPM that uses no information from previous frames.

A robust spike sorting method based on the joint optimization of linear discrimination analysis and density peaks

Spike sorting is a fundamental step in extracting single-unit activity from neural ensemble recordings, which play an important role in basic neuroscience and neurotechnologies. A few algorithms have been applied in spike sorting. However, when noise level or waveform similarity becomes relatively high, their robustness still faces a big challenge. In this study, we propose a spike sorting method combining Linear Discriminant Analysis (LDA) and Density Peaks (DP) for feature extraction and clustering. Relying on the joint optimization of LDA and DP: DP provides more accurate classification labels for LDA, LDA extracts more discriminative features to cluster for DP, and the algorithm achieves high performance after iteration. We first compared the proposed LDA-DP algorithm with several algorithms on one publicly available simulated dataset and one real rodent neural dataset with different noise levels. We further demonstrated the performance of the LDA-DP method on a real neural dataset from non-human primates with more complex distribution characteristics. The results show that our LDA-DP algorithm extracts a more discriminative feature subspace and achieves better cluster quality than previously established methods in both simulated and real data. Especially in the neural recordings with high noise levels or waveform similarity, the LDA-DP still yields a robust performance with automatic detection of the number of clusters. The proposed LDA-DP algorithm achieved high sorting accuracy and robustness to noise, which offers a promising tool for spike sorting and facilitates the following analysis of neural population activity.

Disruption of layer-specific visual processing in a model of focal neocortical epilepsy

The epileptic brain is the result of a sequence of events transforming normal neuronal populations into hyperexcitable networks supporting recurrent seizure generation. These modifications are known to induce fundamental alterations of circuit function and, ultimately, of behavior. However, how hyperexcitability affects information processing in cortical sensory circuits is not yet fully understood. Here, we investigated interlaminar alterations in sensory processing of the visual cortex in a mouse model of focal epilepsy. We found three main circuit dynamics alterations in epileptic mice: (i) a spreading of visual contrast-driven gamma modulation across layers, (ii) an increase in firing rate that is layer-unspecific for excitatory units and localized in infragranular layers for inhibitory neurons, and (iii) a strong and contrast-dependent locking of firing units to network activity. Altogether, our data show that epileptic circuits display a functional disruption of layer-specific organization of visual sensory processing, which could account for visual dysfunction observed in epileptic subjects. Understanding these mechanisms paves the way to circuital therapeutic interventions for epilepsy.

Efficient Approximation of Action Potentials with High-Order Shape Preservation in Unsupervised Spike Sorting

This paper presents a novel approximation unit added to the conventional spike processing chain which provides an appreciable reduction of complexity of the high-hardware cost feature extractors. The use of the Taylor polynomial is proposed and modelled employing its cascaded derivatives to non-uniformly capture the essential samples in each spike for reliable feature extraction and sorting. Inclusion of the approximation unit can provide 3X compression (i.e. from 66 to 22 samples) to the spike waveforms while preserving their shapes. Detailed spike waveform sequences based on in-vivo measurements have been generated using a customized neural simulator for performance assessment of the approximation unit tested on six published feature extractors. For noise levels σ_N between 0.05 and 0.3 and groups of 3 spikes in each channel, all the feature extractors provide almost same sorting performance before and after approximation. The overall implementation cost when including the approximation unit and feature extraction shows a large reduction (i.e. up to 8.7X) in the hardware costly and more accurate feature extractors, offering a substantial improvement in feature extraction design.

A Vector Quantization-Based Spike Compression Approach Dedicated to Multichannel Neural Recording Microsystems

Implantable high-density multichannel neural recording microsystems provide simultaneous recording of brain activities. Wireless transmission of the entire recorded data causes high bandwidth usage, which is not tolerable for implantable applications. As a result, a hardware-friendly compression module is required to reduce the amount of data before it is transmitted. This paper presents a novel compression approach that utilizes a spike extractor and a vector quantization (VQ)-based spike compressor. In this approach, extracted spikes are vector quantized using an unsupervised learning process providing a high spike compression ratio (CR) of 10-80. A combination of extracting and compressing neural spikes results in a significant data reduction as well as preserving the spike waveshapes. The compression performance of the proposed approach was evaluated under variant conditions. We also developed new architectures such that the hardware blocks of our approach can be implemented more efficiently. The compression module was implemented in a 180-nm standard CMOS process achieving a SNDR of 14.49[Formula: see text]dB and a classification accuracy (CA) of 99.62% at a CR of 20, while consuming 4[Formula: see text][Formula: see text]W power and 0.16[Formula: see text]mm² chip area per channel.

An automatic spike sorting algorithm based on adaptive spike detection and a mixture of skew-t distributions

Developing high-density electrodes for recording large ensembles of neurons provides a unique opportunity for understanding the mechanism of the neuronal circuits. Nevertheless, the change of brain tissue around chronically implanted neural electrodes usually causes spike wave-shape distortion and raises the crucial issue of spike sorting with an unstable structure. The automatic spike sorting algorithms have been developed to extract spikes from these big extracellular data. However, due to the spike wave-shape instability, there have been a lack of robust spike detection procedures and clustering to overcome the spike loss problem. Here, we develop an automatic spike sorting algorithm based on adaptive spike detection and a mixture of skew-t distributions to address these distortions and instabilities. The adaptive detection procedure applies to the detected spikes, consists of multi-point alignment and statistical filtering for removing mistakenly detected spikes. The detected spikes are clustered based on the mixture of skew-t distributions to deal with non-symmetrical clusters and spike loss problems. The proposed algorithm improves the performance of the spike sorting in both terms of precision and recall, over a broad range of signal-to-noise ratios. Furthermore, the proposed algorithm has been validated on different datasets and demonstrates a general solution to precise spike sorting, in vitro and in vivo.

A framework for on-implant spike sorting based on salient feature selection

On-implant spike sorting methods employ static feature extraction/selection techniques to minimize the hardware cost. Here we propose a novel framework for real-time spike sorting based on dynamic selection of features. We select salient features that maximize the geometric-mean of between-class distances as well as the associated homogeneity index effectively to best discriminate spikes for classification. Wave-shape classification is performed based on a multi-label window discrimination approach. An external module calculates the salient features and discrimination windows through optimizing a replica of the on-implant operation, and then configures the on-implant spike sorter for real-time online operation. Hardware implementation of the on-implant online spike sorter for 512 channels of concurrent extra-cellular neural signals is reported, with an average classification accuracy of ~88%. Compared with other similar methods, our method shows reduction in classification error by a factor of ~2, and also reduction in the required memory space by a factor of ~5.

Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction

This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.

Accurate, Very Low Computational Complexity Spike Sorting Using Unsupervised Matched Subspace Learning

This paper presents an adaptable dictionary-based feature extraction approach for spike sorting offering high accuracy and low computational complexity for implantable applications. It extracts and learns identifiable features from evolving subspaces through matched unsupervised subspace filtering. To provide compatibility with the strict constraints in implantable devices such as the chip area and power budget, the dictionary contains arrays of {-1, 0 and 1} and the algorithm need only process addition and subtraction operations. Three types of such dictionary were considered. To quantify and compare the performance of the resulting three feature extractors with existing systems, a neural signal simulator based on several different libraries was developed. For noise levels σ_N between 0.05 and 0.3 and groups of 3 to 6 clusters, all three feature extractors provide robust high performance with average classification errors of less than 8% over five iterations, each consisting of 100 generated data segments. To our knowledge, the proposed adaptive feature extractors are the first able to classify reliably 6 clusters for implantable applications. An ASIC implementation of the best performing dictionary-based feature extractor was synthesized in a 65-nm CMOS process. It occupies an area of 0.09 mm² and dissipates up to about 10.48 μW from a 1 V supply voltage, when operating with 8-bit resolution at 30 kHz operating frequency.

Neural signal recording and processing in somatic neuroprosthetic applications. A review

Neurointerfaces have acquired major relevance as both rehabilitative and therapeutic tools for patients with spinal cord injury, limb amputations and other neural disorders. Bidirectional neural interfaces are a key component for the functional control of neuroprosthetic devices. The two main neuroprosthetic applications of interfaces with the peripheral nervous system (PNS) are: the refined control of artificial prostheses with sensory neural feedback, and functional electrical stimulation (FES) systems attempting to generate motor or visceral responses in paralyzed organs. The results obtained in experimental and clinical studies with both, extraneural and intraneural electrodes are very promising in terms of the achieved functionality for the neural stimulation mode. However, the results of neural recordings with peripheral nerve interfaces are more limited. In this paper we review the different existing approaches for PNS signals recording, denoising, processing and classification, enabling their use for bidirectional interfaces. PNS recordings can provide three types of signals: i) population activity signals recorded by using extraneural electrodes placed on the outer surface of the nerve, which carry information about cumulative nerve activity; ii) spike activity signals recorded with intraneural electrodes placed inside the nerve, which carry information about the electrical activity of a set of individual nerve fibers; and iii) hybrid signals, which contain both spiking and cumulative signals. Finally, we also point out some of the main limitations, which are hampering clinical translation of neural decoding, and indicate possible solutions for improvement.

Computationally efficient fully-automatic online neural spike detection and sorting in presence of multi-unit activity for implantable circuits

BACKGROUND

Spike sorting is a basic step for implantable neural interfaces. With the growing number of channels, the process should be computationally efficient, automatic,robust and applicable on implantable circuits.

NEW METHOD

The proposed method is a combination of fully-automatic offline and online processes. It introduces a novel method for automatically determining a data-aware spike detection threshold, computationally efficient spike feature extraction, automatic optimal cluster number evaluation and verification coupled with Self-Organizing Maps to accurately determine cluster centroids. The system has the ability of unsupervised online operation after initial fully-automatic offline training. The prime focus of this paper is to fully-automate the complete spike detection and sorting pipeline, while keeping the accuracy high.

RESULTS

The proposed system is simulated on two well-known datasets. The automatic threshold improves detection accuracies significantly( > 15%) as compared to the most common detector. The system is able to effectively handle background multi-unit activity with improved performance.

COMPARISON

Most of the existing methods are not fully-automatic; they require supervision and expert intervention at various stages of the pipeline. Secondly, existing works focus on foreground neural activity. Recent research has highlighted importance of background multi-unit activity, and this work is amongst the first efforts that proposes and verifies an automatic methodology to effectively handle them as well.

CONCLUSION

This paper proposes a fully-automatic, computationally efficient system for spike sorting for both single-unit and multi-unit spikes. Although the scope of this work is design and verification through computer simulations, the system has been designed to be easily transferable into an integrated hardware form.

Spike sorting based on shape, phase, and distribution features, and K-TOPS clustering with validity and error indices

Spike sorting is one of the most important data analysis problems in neurophysiology. The precision in all steps of the spike-sorting procedure critically affects the accuracy of all subsequent analyses. After data preprocessing and spike detection have been carried out properly, both feature extraction and spike clustering are the most critical subsequent steps of the spike-sorting procedure. The proposed spike sorting approach comprised a new feature extraction method based on shape, phase, and distribution features of each spike (hereinafter SS-SPDF method), which reveal significant information of the neural events under study. In addition, we applied an efficient clustering algorithm based on K-means and template optimization in phase space (hereinafter K-TOPS) that included two integrative clustering measures (validity and error indices) to verify the cohesion-dispersion among spike events during classification and the misclassification of clustering, respectively. The proposed method/algorithm was tested on both simulated data and real neural recordings. The results obtained for these datasets suggest that our spike sorting approach provides an efficient way for sorting both single-unit spikes and overlapping waveforms. By analyzing raw extracellular recordings collected from the rostral-medial prefrontal cortex (rmPFC) of behaving rabbits during classical eyeblink conditioning, we have demonstrated that the present method/algorithm performs better at classifying spikes and neurons and at assessing their modulating properties than other methods currently used in neurophysiology.

Unsupervised and real-time spike sorting chip for neural signal processing in hippocampal prosthesis

BACKGROUND

Damage to the hippocampus will result in the loss of ability to form new long-term memories and cognitive disorders. At present, there is no effective medical treatment for this issue. Hippocampal cognitive prosthesis is proposed to replace damaged regions of the hippocampus to mimic the function of original biological tissue. This prosthesis requires a spike sorter to detect and classify spikes in the recorded neural signal.

NEW METHOD

A 16-channel spike sorting processor is presented in this paper, where all channels are considered as independent. An automatic threshold estimation method suitable for hardware implementation is proposed for the Osort clustering algorithm. A new distance metric is also introduced to facilitate clustering. Bayes optimal template matching classification algorithm is optimized to reduce computational complexity by introducing a preselection mechanism.

RESULTS

The chip was fabricated in 40-nm CMOS process with a core area of 0.0175 mm²/ch and power consumption of 19.0 μW/ch. Synthetic and realistic test data are used to evaluate the chip. The test result shows that it has high performance on both data.

COMPARISON WITH EXISTING METHOD(S)

Compared with the other three spike sorting processors, the proposed chip achieves the highest detection and classification accuracy. It also has the ability to deal with partially overlapping spikes, which is not reported in the other work.

CONCLUSIONS

We have developed a 16-channel spike sorting chip used in hippocampal prosthesis, which provides unsupervised clustering and real-time detection and classification. It also has the ability to deal with partially overlapping spikes.

A Streaming PCA VLSI Chip for Neural Data Compression

Neural recording system miniaturization and integration with low-power wireless technologies require compressing neural data before transmission. Feature extraction is a procedure to represent data in a low-dimensional space; its integration into a recording chip can be an efficient approach to compress neural data. In this paper, we propose a streaming principal component analysis algorithm and its microchip implementation to compress multichannel local field potential (LFP) and spike data. The circuits have been designed in a 65-nm CMOS technology and occupy a silicon area of 0.06 mm. Throughout the experiments, the chip compresses LFPs by 10 at the expense of as low as 1% reconstruction errors and 144-nW/channel power consumption; for spikes, the achieved compression ratio is 25 with 8% reconstruction errors and 3.05-W/channel power consumption. In addition, the algorithm and its hardware architecture can swiftly adapt to nonstationary spiking activities, which enables efficient hardware sharing among multiple channels to support a high-channel count recorder.

Event-driven processing for hardware-efficient neural spike sorting

OBJECTIVE

The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing.

APPROACH

(1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability.

MAIN RESULTS

It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources.

SIGNIFICANCE

By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

A Hardware-Efficient Scalable Spike Sorting Neural Signal Processor Module for Implantable High-Channel-Count Brain Machine Interfaces

Next-generation brain machine interfaces demand a high-channel-count neural recording system to wirelessly monitor activities of thousands of neurons. A hardware efficient neural signal processor (NSP) is greatly desirable to ease the data bandwidth bottleneck for a fully implantable wireless neural recording system. This paper demonstrates a complete multichannel spike sorting NSP module that incorporates all of the necessary spike detector, feature extractor, and spike classifier blocks. To meet high-channel-count and implantability demands, each block was designed to be highly hardware efficient and scalable while sharing resources efficiently among multiple channels. To process multiple channels in parallel, scalability analysis was performed, and the utilization of each block was optimized according to its input data statistics and the power, area and/or speed of each block. Based on this analysis, a prototype 32-channel spike sorting NSP scalable module was designed and tested on an FPGA using synthesized datasets over a wide range of signal to noise ratios. The design was mapped to 130 nm CMOS to achieve 0.75 μW power and 0.023 mm² area consumptions per channel based on post synthesis simulation results, which permits scalability of digital processing to 690 channels on a 4×4 mm² electrode array.

A 400 MHz Wireless Neural Signal Processing IC With 625 $\times$ On-Chip Data Reduction and Reconfigurable BFSK/QPSK Transmitter Based on Sequential Injection Locking

An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, and feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK transmitter (TX) at MICS/MedRadio band is incorporated to support different data rate requirement. By using an Exponential Component-Polynomial Component (EC-PC) spike processing unit with an incremental principal component analysis (IPCA) engine, the detection of neural spikes with poor SNR is possible while achieving 625× data reduction. For the TX, a dual-channel at 401 MHz and 403.8 MHz are supported by applying sequential injection locked techniques while attaining phase noise of -102 dBc/Hz at 100 kHz offset. From the measurement, error vector magnitude (EVM) of 4.60%/9.55% with power amplifier (PA) output power of -15 dBm is achieved for the QPSK at 8 Mbps and the BFSK at 12.5 kbps. Fabricated in 65 nm CMOS with an active area of 1 mm ², the design consumes a total current of 5  ∼ 5.6 mA with a maximum energy efficiency of 0.7 nJ/b.

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor

This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Computationally efficient feature denoising filter and selection of optimal features for noise insensitive spike sorting

Feature extraction is a critical step in real-time spike sorting after a spike is detected. Features should be informative and noise insensitive for high classification accuracy. This paper describes a new feature extraction method that utilizes a feature denoising filter to improve noise immunity while preserving spike information. Six features were extracted from filtered spikes, including a newly developed feature, and a separability index was applied to select optimal features. Using a set of the three highest-performing features, which includes the new feature, this method can achieve spike classification error as low as 5% for the worst case noise level of 0.2. The computational complexity is only 11% of principle component analysis method and it only costs nine registers per channel.

A 0.7 V, 40 nW Compact, Current-Mode Neural Spike Detector in 65 nm CMOS

In this paper, we describe a novel low power, compact, current-mode spike detector circuit for real-time neural recording systems where neural spikes or action potentials (AP) are of interest. Such a circuit can enable massive compression of data facilitating wireless transmission. This design can generate a high signal-to-noise ratio (SNR) output by approximating the popularly used nonlinear energy operator (NEO) through standard analog blocks. We show that a low pass filter after the NEO can be used for two functions-(i) estimate and cancel low frequency interference and (ii) estimate threshold for spike detection. The circuit is implemented in a 65 nm CMOS process and occupies 200 μm × 150 μ m of chip area. Operating from a 0.7 V power supply, it consumes about 30 nW of static power and 7 nW of dynamic power for 100 Hz input spike rate making it the lowest power consuming spike detector reported so far.

A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition

In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm (2) for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.

A feature design framework for hardware efficient neural spike sorting

We propose a feature design framework that considers simultaneously performance and computational complexity. In particular, we incorporate these two metrics, which are very important to many low-energy on-chip applications such as implantable neural interfaces, onto an optimization problem. This allows us to strike a balance between the performance of the signal processing task and the computational complexity of the feature extraction process. Simulation results for neural spike sorting demonstrate that by leveraging proposed design framework, we can construct features that outperform other state-of-the-art, low-complexity feature designs, both in terms of classification error and complexity.

The Principle of the Micro-Electronic Neural Bridge and a Prototype System Design

The micro-electronic neural bridge (MENB) aims to rebuild lost motor function of paralyzed humans by routing movement-related signals from the brain, around the damage part in the spinal cord, to the external effectors. This study focused on the prototype system design of the MENB, including the principle of the MENB, the neural signal detecting circuit and the functional electrical stimulation (FES) circuit design, and the spike detecting and sorting algorithm. In this study, we developed a novel improved amplitude threshold spike detecting method based on variable forward difference threshold for both training and bridging phase. The discrete wavelet transform (DWT), a new level feature coefficient selection method based on Lilliefors test, and the k-means clustering method based on Mahalanobis distance were used for spike sorting. A real-time online spike detecting and sorting algorithm based on DWT and Euclidean distance was also implemented for the bridging phase. Tested by the data sets available at Caltech, in the training phase, the average sensitivity, specificity, and clustering accuracies are 99.43%, 97.83%, and 95.45%, respectively. Validated by the three-fold cross-validation method, the average sensitivity, specificity, and classification accuracy are 99.43%, 97.70%, and 96.46%, respectively.

Minimum requirements for accurate and efficient real-time on-chip spike sorting

BACKGROUND

Extracellular recordings are performed by inserting electrodes in the brain, relaying the signals to external power-demanding devices, where spikes are detected and sorted in order to identify the firing activity of different putative neurons. A main caveat of these recordings is the necessity of wires passing through the scalp and skin in order to connect intracortical electrodes to external amplifiers. The aim of this paper is to evaluate the feasibility of an implantable platform (i.e., a chip) with the capability to wirelessly transmit the neural signals and perform real-time on-site spike sorting.

NEW METHOD

We computationally modelled a two-stage implementation for online, robust, and efficient spike sorting. In the first stage, spikes are detected on-chip and streamed to an external computer where mean templates are created and sent back to the chip. In the second stage, spikes are sorted in real-time through template matching.

RESULTS

We evaluated this procedure using realistic simulations of extracellular recordings and describe a set of specifications that optimise performance while keeping to a minimum the signal requirements and the complexity of the calculations.

COMPARISON WITH EXISTING METHODS

A key bottleneck for the development of long-term BMIs is to find an inexpensive method for real-time spike sorting. Here, we simulated a solution to this problem that uses both offline and online processing of the data.

CONCLUSIONS

Hardware implementations of this method therefore enable low-power long-term wireless transmission of multiple site extracellular recordings, with application to wireless BMIs or closed-loop stimulation designs.

A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants

This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

Efficient architecture for spike sorting in reconfigurable hardware

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.