Data Compression Versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording

Future high-density and high channel count neural interfaces that enable simultaneous recording of tens of thousands of neurons will provide a gateway to study, restore and augment neural functions. However, building such technology within the bit-rate limit and power budget of a fully implantable device is challenging. The wired-OR compressive readout architecture addresses the data deluge challenge of a high channel count neural interface using lossy compression at the analog-to-digital interface. In this article, we assess the suitability of wired-OR for several steps that are important for neuroengineering, including spike detection, spike assignment and waveform estimation. For various wiring configurations of wired-OR and assumptions about the quality of the underlying signal, we characterize the trade-off between compression ratio and task-specific signal fidelity metrics. Using data from 18 large-scale microelectrode array recordings in macaque retina ex vivo, we find that for an event SNR of 7-10, wired-OR correctly detects and assigns at least 80% of the spikes with at least 50× compression. The wired-OR approach also robustly encodes action potential waveform information, enabling downstream processing such as cell-type classification. Finally, we show that by applying an LZ77-based lossless compressor (gzip) to the output of the wired-OR architecture, 1000× compression can be achieved over the baseline recordings.

Intertwined-pulse modulation for compressive data telemetry

This paper presents a novel approach for anisochronous pulse-based modulation. In the proposed approach, referred to as the intertwined-pulse modulation (IPM), every pair of consecutive symbols overlap in time. This allows for shortening the time allocated for the transmission of the symbols, hence achieving temporal compaction while the data goes through the line encoding step in a digital communication system. The IPM is also uniquely superior to other existing anisochronous pulse-based modulation schemes in the fact that it exhibits robust symbol error rate against unwanted variations in both rise/fall times of the pulses in the modulated waveform, and in the threshold level used for data detection on the receiver side. An experimental setup was developed to implement an IPM encoder using standard digital hardware, and an IPM decoder as a part of the receiver system in software. According to the experimental results (supported by simulation results and theoretical studies), for the data mean value of mid-full-scale range, the proposed IPM scheme exhibits a time-domain compaction rate of up to 209.2%.

A Vector Quantization-Based Spike Compression Approach Dedicated to Multichannel Neural Recording Microsystems

Implantable high-density multichannel neural recording microsystems provide simultaneous recording of brain activities. Wireless transmission of the entire recorded data causes high bandwidth usage, which is not tolerable for implantable applications. As a result, a hardware-friendly compression module is required to reduce the amount of data before it is transmitted. This paper presents a novel compression approach that utilizes a spike extractor and a vector quantization (VQ)-based spike compressor. In this approach, extracted spikes are vector quantized using an unsupervised learning process providing a high spike compression ratio (CR) of 10-80. A combination of extracting and compressing neural spikes results in a significant data reduction as well as preserving the spike waveshapes. The compression performance of the proposed approach was evaluated under variant conditions. We also developed new architectures such that the hardware blocks of our approach can be implemented more efficiently. The compression module was implemented in a 180-nm standard CMOS process achieving a SNDR of 14.49[Formula: see text]dB and a classification accuracy (CA) of 99.62% at a CR of 20, while consuming 4[Formula: see text][Formula: see text]W power and 0.16[Formula: see text]mm² chip area per channel.

Spatial Redundancy Reduction in Multi-Channel Implantable Neural Recording Microsystems

This paper introduces a lossless approach for data reduction in multi-channel neural recording microsystems. The proposed approach benefits from eliminating the redundancy that exists in the signals recorded from the same space in the brain, e.g., local field potentials in intra-cortical recording from neighboring recording sites. In this approach, a single baseline component is extracted from the original neural signals, which is treated as the component all the channels share in common. What remains is a set of channel-specific difference components, which are much smaller in word length compared to the sample size of the original neural signals. To make the proposed approach more efficient in data reduction, length of the difference component words is adaptively determined according to their instantaneous amplitudes. This approach is low in both computational and hardware complexity, which introduces it as an attractive suggestion for high-density neural recording brain implants. Applied on multi-channel neural signals intra-cortically recorded using 16 multi-electrode array, the data is reduced by around 48%. Designed in TSMC 130-nm standard CMOS technology, hardware implementation of this technique for 16 parallel channels occupies a silicon area of 0.06 mm², and dissipates 6.4 μW of power per channel when operates at V_DD=1.2V and 400 kHz.Clinical Relevance- This paper presents a lossless data reduction technique, dedicated to brain-implantable neural recording devices. Such devices are developed for clinical applications such as the treatment of epilepsy, neuro-prostheses, and brain-machine interfacing for therapeutic purposes.

Hardware and Power-Efficient Compression Technique Based on Discrete Tchebichef Transform for Neural Recording Microsystems

In this paper a new compression technique based on the discrete Tchebichef transform is presented. To comply with strict on-implant hardware implementation requirements, such as low power dissipation and small silicon area consumption, the discrete Tchebichef transform is modified and truncated. An algorithm is proposed to generate approximate transform matrices capable of truncation without suffering from destructive energy leakage among the coefficients. This is achieved by preserving orthogonality of the basis functions that convey majority portion of the signal energy. Based on the presented algorithm, a new truncated transformation matrix is proposed, which reduces the hardware complexity by up to 74% compared to that of the original transform. Hardware implementation of the proposed neural signal compression technique is prototyped using standard digital hardware. With pre-recorded neural signals as the input, compression rate of 26.15 is achieved while the root-mean-square of error is kept as low as 1.1%.Clinical Relevance- This paper proposes a technique for data compression in high-density neural recording brain implants, along with a power- and area-efficient hardware implementation. From among clinical applications of such implants one can point to neuro-prostheses, and brain-machine interfaces for therapeutic purposes.

Spike Detection Technique Based on Spike Augmentation with Low Computational and Hardware Complexity

In this paper, a method for the detection and subsequently extraction of neural spikes in an intra-cortically recorded neural signal is proposed. This method distinguishes spikes from the background noise based on the natural difference between their time-domain amplitude variation patterns. According to this difference, a spike mask is generated, which takes on large values over the course of spikes, and much smaller values for the background noise. The "high" part of this mask is designed to be wide enough to contain a complete spike. By multiplying the input neural signal with the spike mask, spikes are amplified with a large factor while the background noise is not. The result is a spike-augmented signal with significantly larger signal-to-noise ratio, on which spike detection is performed much more easily and accurately. According to this detection mechanism, spikes of the original neural signal are extracted.Clinical Relevance-This paper presents an automatic spike detection technique, dedicated to brain-implantable neural recording devices. Such devices are developed for clinical applications such as the treatment of epilepsy, neuro-prostheses, and brain-machine interfacing for therapeutic purposes.

A framework for on-implant spike sorting based on salient feature selection

On-implant spike sorting methods employ static feature extraction/selection techniques to minimize the hardware cost. Here we propose a novel framework for real-time spike sorting based on dynamic selection of features. We select salient features that maximize the geometric-mean of between-class distances as well as the associated homogeneity index effectively to best discriminate spikes for classification. Wave-shape classification is performed based on a multi-label window discrimination approach. An external module calculates the salient features and discrimination windows through optimizing a replica of the on-implant operation, and then configures the on-implant spike sorter for real-time online operation. Hardware implementation of the on-implant online spike sorter for 512 channels of concurrent extra-cellular neural signals is reported, with an average classification accuracy of ~88%. Compared with other similar methods, our method shows reduction in classification error by a factor of ~2, and also reduction in the required memory space by a factor of ~5.

Spike detection and spike sorting with a hidden Markov model improves offline decoding of motor cortical recordings

OBJECTIVE

Detection and sorting (classification) of action potentials from extracellular recordings are two important pre-processing steps for brain-computer interfaces (BCIs) and some neuroscientific studies. Traditional approaches perform these two steps serially, but using shapes of action potential waveforms during detection, i.e. combining the two steps, may lead to better performance, especially during high noise. We propose a hidden Markov model (HMM) based method for combined detecting and sorting of spikes, with the aim of improving the final decoding accuracy of BCIs.

APPROACH

The states of the HMM indicate whether there is a spike, what unit a spike belongs to, and the time course within a waveform. The HMM outputs probabilities of spike detection, and from this we can calculate expectations of spike counts in time bins, which can replace integer spike counts as input to BCI decoders. We evaluate the HMM method on simulated spiking data. We then examine the impact of using this method on decoding real neural data recorded from primary motor cortex of two Rhesus monkeys.

MAIN RESULTS

Our comparisons on simulated data to detection-then-sorting approaches and combined detection-and-sorting algorithms indicate that the HMM method performs more accurately at detection and sorting (0.93 versus 0.73 spike count correlation, 0.73 versus 0.49 adjusted mutual information). On real neural data, the HMM method led to higher adjusted mutual information between spike counts and kinematics (monkey K: 0.034 versus 0.027; monkey M: 0.033 versus 0.022) and better neuron encoding model predictions (K: 0.016 dB improvement; M: 0.056 dB improvement). Lastly, the HMM method facilitated higher offline decoding accuracy (Kalman filter, K: 8.5% mean squared error reduction, M: 18.6% reduction).

SIGNIFICANCE

The HMM spike detection and sorting method offers a new approach to spike pre-processing for BCIs and neuroscientific studies.

A Streaming PCA VLSI Chip for Neural Data Compression

Neural recording system miniaturization and integration with low-power wireless technologies require compressing neural data before transmission. Feature extraction is a procedure to represent data in a low-dimensional space; its integration into a recording chip can be an efficient approach to compress neural data. In this paper, we propose a streaming principal component analysis algorithm and its microchip implementation to compress multichannel local field potential (LFP) and spike data. The circuits have been designed in a 65-nm CMOS technology and occupy a silicon area of 0.06 mm. Throughout the experiments, the chip compresses LFPs by 10 at the expense of as low as 1% reconstruction errors and 144-nW/channel power consumption; for spikes, the achieved compression ratio is 25 with 8% reconstruction errors and 3.05-W/channel power consumption. In addition, the algorithm and its hardware architecture can swiftly adapt to nonstationary spiking activities, which enables efficient hardware sharing among multiple channels to support a high-channel count recorder.